The SCEAS System
Navigation Menu

Conferences in DBLP

IEEE International Symposium on Multiple-Valued Logic (ISMVL) (ismvl)
2002 (conf/ismvl/2002)

  1. Sergiu Rudeanu
    Equations in the Algebra of Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:2-0 [Conf]
  2. Hajime Machida, Masahiro Miyakawa, Ivo G. Rosenberg
    Some Results on the Centralizers of Monoids in Clone Theory. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:10-16 [Conf]
  3. B. A. Romov
    Partial Hyperclones on a Finite Set. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:17-22 [Conf]
  4. Michiro Kondo
    On the Structures of Weak Interlaced Bilattice. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:23-0 [Conf]
  5. Claudio Moraga
    Improving the Characterization of p-Valued Threshold Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:28-34 [Conf]
  6. Elena Dubrova, Petra Färm
    A Conjunctive Canonical Expansion of Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:35-38 [Conf]
  7. Denis V. Popel, Anita Dani
    Sierpinski Gaskets for Logic Functions Representation. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:39-45 [Conf]
  8. Noboru Takagi, Kyoichi Nakashima
    Logic for Static Hazard Detection of Multiple-Valued Logic Circuits with Tsum, Min, and Literals. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:46-0 [Conf]
  9. Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi
    Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:54-60 [Conf]
  10. Takao Waho, Shin-ya Kobayashi, Koji Matsuura
    An Impact of Introducing Multi-Level Signals to a Bandpass Cascaded Delta-Sigma Modulator. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:61-66 [Conf]
  11. Yongjian Brandon Guo, K. Wayne Current
    Voltage Comparator Circuits for Multiple-Valued CMOS Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:67-0 [Conf]
  12. Dragan Jankovic, Radomir S. Stankovic
    Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multiple-Valued Logic Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:76-82 [Conf]
  13. K. J. Adams, J. McGregor
    Comparison of Different Features of Quaternary Reed-Muller Canonical Forms and Some New Statistical Results. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:83-88 [Conf]
  14. Boris Polianskikh, Zeljko Zilic
    Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:89-95 [Conf]
  15. Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
    Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:96-0 [Conf]
  16. Vincenzo Marra, Daniele Mundici
    Consequence and Complexity in Infinite-Valued Logic: A Survey. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:104-0 [Conf]
  17. Radomir S. Stankovic, Jaakko Astola
    Some Remarks on Linear Transform of Variables in Representation of Adders by Word-Level Expressions and Spectral Transform Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:116-122 [Conf]
  18. Mitchell A. Thornton, D. Michael Miller, Whitney J. Townsend
    Chrestenson Spectrum Computation Using Cayley Color Graphs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:123-129 [Conf]
  19. Zeljko Zilic, Katarzyna Radecka
    The Role of Super-Fast Transforms in Speeding Up Quantum Computations. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:129-135 [Conf]
  20. Bogdan J. Falkowski, Beata T. Olejnicka
    Multiple-Valued and Spectral Approach to Lossless Compression of Binary, Gray Scale and Color Biomedical Images. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:136-0 [Conf]
  21. Elena N. Zaitseva, Vitaly G. Levashenko
    Design of Dynamic Reliability Indices. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:144-148 [Conf]
  22. Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui
    PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:149-155 [Conf]
  23. Yinshui Xia, Xunwei Wu, Penjung Wang
    Design of Ternary Schmitt Triggers Based on Its Sequential Characteristics. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:156-160 [Conf]
  24. Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama
    Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:161-0 [Conf]
  25. Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa
    Optimization of Multi-Valued Multi-Level Networks. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:168-0 [Conf]
  26. Hiroaki Kikuchi, Noboru Takagi
    de Morgan Bisemilattice of Fuzzy Truth Value. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:180-184 [Conf]
  27. Tomoko Ninomiya, Masao Mukaidono
    Independence of Each Axiom in a Set of Axioms and Complete Sets of Axioms of Boolean Algebra. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:185-191 [Conf]
  28. Ivo G. Rosenberg, Dan A. Simovici, Szymon Jaroszewicz
    On Functions Defined on Free Boolean Algebras. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:192-0 [Conf]
  29. Svetlana N. Yanushkevich, Piotr Dziurzanski, Vlad P. Shmerko
    The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 1: LAR Based Model. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:202-208 [Conf]
  30. Anna M. Tomaszewska, Svetlana N. Yanushkevich, Vlad P. Shmerko
    The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 2: LWL Based Model. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:209-215 [Conf]
  31. Ilia Polian, Piet Engelke, Bernd Becker
    Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:216-0 [Conf]
  32. Naofumi Takagi
    Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:224-0 [Conf]
  33. Masahiro Miyakawa, Nobuyuki Otsu, Ivo G. Rosenberg
    Variable Selection Heuristics and Optimum Decision Trees - An Experimental Study. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:238-244 [Conf]
  34. D. Michael Miller, Rolf Drechsler
    On the Construction of Multiple-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:245-253 [Conf]
  35. Rolf Drechsler
    Evaluation of Static Variable Ordering Heuristics for MDD Construction. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:254-260 [Conf]
  36. Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura
    Representations of Logic Functions Using QRMDDs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:261-0 [Conf]
  37. Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama
    Fully Source-Coupled Logic Based Multiple-Valued VLSI. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:270-275 [Conf]
  38. Sung Il Han, Seung-Yong Park, Hyeon Kyeong Seong, Heung-Soo Kim
    A Current-Mode Folding/Interpolating CMOS Analog to Quaternary Converter Using Binary to Quaternary Encoding Block. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:276-281 [Conf]
  39. Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
    Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:282-0 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002