Conferences in DBLP
Carl-Johan H. Seger , Randal E. Bryant Digital Circuit Verification Using Partially-Ordered State Models. [Citation Graph (0, 0)][DBLP ] Conf ] A. Kazeminejad , K. Navi , Daniel Etiemble CML Current Mode Full Adders for 2.5-V Power Supply. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Shang Chu , K. Wayne Current Quaternary Multiplier Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Hanyu , Akira Mochizuki , Michitaka Kameyama Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. [Citation Graph (0, 0)][DBLP ] Conf ] K. Navi , A. Kazeminejad , Daniel Etiemble Performance of CMOS Current Mode Full Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Yeong-Jar Chang , Chung-Len Lee Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Hui Min Wang , Chung-Len Lee , Jwu E. Chen Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yutaka Hata , Kazuharu Yamato A Multiple-Valued Logic Synthesis Using the Kleenean Coefficients. [Citation Graph (0, 0)][DBLP ] Conf ] Gamal H. Abdel-Hamid , Mostafa H. Abd-El-Barr Decomposition-Based Synthesis of Multiple-Valued Functions for Threshold Logic Network Realization. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Becker , Rolf Drechsler Efficient Graph Based Representation of Multi-Valued Functions with an Application to Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Gerhard W. Dueck , Jon T. Butler Multiple-Valued Logic Operations with Universal Literals. [Citation Graph (0, 0)][DBLP ] Conf ] Radomir S. Stankovic , Milena Stankovic , Claudio Moraga , Tsutomu Sasao Calculation of Reed-Muller-Fourier Coefficients of Multiple-Valued Functions through Multiple-Place Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] D. Michael Miller Spectral Transformation of Multiple-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Sasao , Jon T. Butler A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion. [Citation Graph (0, 0)][DBLP ] Conf ] Zbigniew Stachniak Lattices of Resolution Logics. [Citation Graph (0, 0)][DBLP ] Conf ] Anavai Ramesh , Neil V. Murray Computing Prime Implicants/Implicates for Regular Logics. [Citation Graph (0, 0)][DBLP ] Conf ] Noboru Takagi , Kyoichi Nakashima , Masao Mukaidono Minimization for Kleene-Stone Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Claudio Moraga , J. Cañas , R. Monge , Luis Salinas , M. Gómez Parallel Processing of Fuzzy Inferences. [Citation Graph (0, 0)][DBLP ] Conf ] Alireza Kaviani , Zvonko G. Vranesic On Scheduling in Multiprocessor Systems Using Fuzzy Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Edmund Pierzchala , Marek A. Perkowski , Stan Grygiel A Filed Programmable Analog Array for Continuous, Fuzzy, and Multi-Valued Logic Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Tang , Hung Chang Lin , Sen Jung Wei Multi-Peak Resonant Tunneling Diodes Based Fuzzifiers. [Citation Graph (0, 0)][DBLP ] Conf ] János Demetrovics , Corina Reischer , Dan A. Simovici , Ivan Stojmenovic Enumeration of Function and Bases of Three-Valued Set Logic under compositions with Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Feb J. Cabrasawan , T. C. Wesselkamper Searching for Complete Functions over E(3) with Small Radii. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan Stojmenovic Completeness Criteria in Many-Valued Set Logic under Compositions with Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] B. A. Romov The Completeness Problem on the Product of Algebras of Finite-Valued Logic. [Citation Graph (0, 0)][DBLP ] Conf ] H. C. Lin Resonant Tunneling Diodes for Multi-Valued Digital Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Lutz J. Micheel , Hans L. Hartnagel , Wallace T. Anderson , Stephen W. Kirchoefer , Nicolas A. Papanicolaou Interband-Tunneling III-V Semiconductor Structures for Multiple-Valued Literal and Arithmetic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Yasushi Yuminaka , Takafumi Aoki , Tatsuo Higuchi Design of Wave-Parallel Computing Circuits for Densely Connected Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Masami Nakajima , Michitaka Kameyama Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k -Ary Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Takimoto , Takafumi Aoki , Tatsuo Higuchi Design of Multiplex Interconnection Networks for Massively Parallel Computing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner Hähnle Efficient Deduction in Many-Valued Logics. [Citation Graph (0, 0)][DBLP ] Conf ] Gonzalo Escalada-Imaz , Felip Manyà The Satisfiability Problem in Multiple-Valued Horn Formulae. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Baaz , Richard Zach Approximating Propositional Calculi by Finite-Valued Logics. [Citation Graph (0, 0)][DBLP ] Conf ] Helmut Thiele On T-Quantifiers and S-Quantifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Zhao Wu , Hong-Yan Tan An Algebraic Method to Decide the Deduction Problem in Many-Valued Propositional Calculus. [Citation Graph (0, 0)][DBLP ] Conf ] Elie Sanchez Soft Computing Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Elena Dubrova , Dilian Gurov , Jon C. Muzio Full Sensitivity and Test Generation for Multiple-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hui Min Wang , Chung-Len Lee , Jwu E. Chen Complete Test Set for Multiple-Valued Logic Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Naotake Kamiura , Yutaka Hata , Kazuharu Yamato Design of Fault-Tolerant Cellular Arrays on Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Grant Pogosyan , Akihiro Nozaki , Masahiro Miyakawa , Ivo G. Rosenberg Hereditary Clones of Mulitple Valued Logic Algebra. [Citation Graph (0, 0)][DBLP ] Conf ] Graham C. Denham Many-Valued Generalizations of Two Finite Intervals in Post's Lattice. [Citation Graph (0, 0)][DBLP ] Conf ] Corina Reischer , Dan A. Simovici , Ivan Stojmenovic Several Remarks on Algebraic Entropy. [Citation Graph (0, 0)][DBLP ] Conf ] Benchu Fei , Qinghua Hong , Gongli Zhang Identification of Linear Ternary Logic Functions and Its Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Louis H. Kauffman Knot Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Marek A. Perkowski , Malgorzata Chrzanowska-Jeske Multiple-Valued-Input TANT Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jon T. Butler , Tsutomu Sasao Multiple-Valued Combinational Circuits with Feedback. [Citation Graph (0, 0)][DBLP ] Conf ] Yasunori Nagata , Masao Mukaidono On Multiple-Valued Separable Unordered Codes. [Citation Graph (0, 0)][DBLP ] Conf ] George Epstein A Weak Propositional Calculus for Signal Processing with Thresholds. [Citation Graph (0, 0)][DBLP ] Conf ] Mou Hu A Four-Valued Logic and Switch-Level Differences. [Citation Graph (0, 0)][DBLP ] Conf ] 