Conferences in DBLP
Jens Kargaard Madsen , Stephen I. Long A High-Speed Interconnect Network Using Ternary Logic. [Citation Graph (0, 0)][DBLP ] Conf ] S. Sakurai , Takafumi Aoki , Tatsuo Higuchi Wire-Free Computing Circuits Using Optical Wave-Casting. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Ohi , Takafumi Aoki , Tatsuo Higuchi Redundant Complex Number Systems. [Citation Graph (0, 0)][DBLP ] Conf ] M. Ryu , Michitaka Kameyama Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Sasao , Jon T. Butler Planar Multiple-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Zeljko Zilic , Zvonko G. Vranesic Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. [Citation Graph (0, 0)][DBLP ] Conf ] R. Oenning , Claudio Moraga Properties of the Zhang-Watari Transform. [Citation Graph (0, 0)][DBLP ] Conf ] K. Wayne Current Memory Circuits for Multiple-Valued Logic Voltage Signals. [Citation Graph (0, 0)][DBLP ] Conf ] K. Navi , Daniel Etiemble From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Hanyu , Akira Mochizuki , Michitaka Kameyama Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. [Citation Graph (0, 0)][DBLP ] Conf ] J. Beckman , T. C. Wesselkamper The Radii of Sheffer Functions Over E(3). [Citation Graph (0, 0)][DBLP ] Conf ] Alioune Ngom , Corina Reischer , Ivan Stojmenovic Classification of Functions and Enumeration of Bases of Set Logic under Boolean Compositions. [Citation Graph (0, 0)][DBLP ] Conf ] B. A. Romov Completeness Theory for Vector Partial Multiple-Valued Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaowei Deng , Takahiro Hanyu , Michitaka Kameyama Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Drechsler , Rolf Krieger , Bernd Becker Random Pattern Fault Simulation in Multi-Valued Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Elena Dubrova , Dilian Gurov , Jon C. Muzio The Evaluation of Full Sensitivity for Test Generation in MVL Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zuoquan Lin Paraconsistent Circumscription: First-Order Case. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan J. Falkowski , Susanto Rahardja Novel Quantized Transform for Ternary Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Seiki Akama , Y. Nakayama A Three-Valued Semantics for Discourse Representations. [Citation Graph (0, 0)][DBLP ] Conf ] Takao Waho Resonant Tunneling Transistor and Its Application to Multiple-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Helmut Thiele On the Mutual Definability of Fuzzy Tolerance Relations and Fuzzy Tolerance Coverings. [Citation Graph (0, 0)][DBLP ] Conf ] N. Schmechel On Lattice-Isomorphism Between Fuzzy Equivalence Relations and Fuzzy Partitions. [Citation Graph (0, 0)][DBLP ] Conf ] Liusheng Liu , Zhijian Li , Bingxue Shi Segment Matrix Vector Quantization and Fuzzy Logic for Isolated-Word Speech Recognition. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan J. Falkowski , Susanto Rahardja Efficient Algorithm for the Generation of Fixed Polarity Quaternary Reed-Muller Expansions. [Citation Graph (0, 0)][DBLP ] Conf ] Hui Min Wang , Chung-Len Lee , Jwu E. Chen Factorization of Multi-Valued Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Yutaka Hata , Naotake Kamiura , Kazuharu Yamato On Input Permutation Technique for Multiple-Valued Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Shoujue Wang , Xunwei Wu , Hongjuan Feng The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Tang , Hung Chang Lin A Fuzzy Membership Function Circuit Using Hysteretic Resonant Tunneling Diodes. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Len Lee , Horng Nan Chern , Min Shung Liao , Hui Min Wang On Designing of 4-Valued Memory with Double-Gate TFT. [Citation Graph (0, 0)][DBLP ] Conf ] Grant Pogosyan , Akihiro Nozaki Join-Irreducible Clones of Multiple-Valued Logic Algebra. [Citation Graph (0, 0)][DBLP ] Conf ] Hajime Machida Finitary Approximations and Metric Structure of the Space of Clones. [Citation Graph (0, 0)][DBLP ] Conf ] Wendy MacCaull Finite Algebraic Models for Residuated Logic. [Citation Graph (0, 0)][DBLP ] Conf ] A. K. Jain , Mostafa H. Abd-El-Barr , R. J. Bolton Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Xunwei Wu , Xiexiong Chen , Jizhong Shen Race-Hazard and Skip-Hazard in Multivalued Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] R. Murakami , Yoshiteru Ohkura , Ryosaku Shimada 2k -ary Cyclic AN Codes for Burst Error Correction. [Citation Graph (0, 0)][DBLP ] Conf ] Noboru Takagi , Hiroaki Kikuchi , Kyoichi Nakashima , Masao Mukaidono A Characterization of Kleenean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Kikuchi , Noboru Takagi , Shohachiro Nakanishi , Masao Mukaidono Uniqueness of Partially Specified Multiple-Valued Kleenean Function. [Citation Graph (0, 0)][DBLP ] Conf ] Zuoquan Lin , Wei Li On Logic of Paradox. [Citation Graph (0, 0)][DBLP ] Conf ] Tadeusz Luba Decomposition of Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] Conf ] T. C. Wesselkamper , J. Danowitz Some New Results for Multiple-Valued Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Zheng Tang , Okihiko Ishizuka , Koichi Tanno Learning Multiple-Valued Logic Networks Based on Back Propagation. [Citation Graph (0, 0)][DBLP ] Conf ] Seiki Akama Three-Valued Constructive Logic and Logic Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Radomir S. Stankovic Functional Decision Diagrams for Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Hozumi , Naotake Kamiura , Yutaka Hata , Kazuharu Yamato Multiple-Valued Logic Design Using Multiple-Valued EXOR. [Citation Graph (0, 0)][DBLP ] Conf ] 