Conferences in DBLP
Adit D. Singh Integrating Yield, Test and Reliability: "Statistical Models with Applications to Test and Burn-in Optimization". [Citation Graph (0, 0)][DBLP ] Conf ] Israel Koren , Julie D. Segal Optimizing the Yield of VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zoran Stamenkovic Testing and Yield of Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Duane S. Boning Test Structures for Circuit Yield Assessment and Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Enrico Malavasi Design Based Yield Improvements (DBYI). [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe Crisenza Yield in flash memory: Methodology, modeling and design issues. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Casale-Rossi Enhancing the Silicon-Package Interface Through Their Concurrent Design and Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Anna Fontanelli An EDA Perspective, "We Need it Yesterday! [Citation Graph (0, 0)][DBLP ] Conf ] Kevin Rinebold An EDA Perspective, "Let's do it Concurrently! [Citation Graph (0, 0)][DBLP ] Conf ] Rich Evans A Package Design Perspective, "It will be BGA and Flip-Chip". [Citation Graph (0, 0)][DBLP ] Conf ] Mohsen Alavi Overview of Reliability Issues in Deep Sub-Micron Digital CMOS Technology and Their Interaction with Circuit Design Considerations. [Citation Graph (0, 0)][DBLP ] Conf ] Ken Tseng Noise Analysis for 0.13um and Beyond. [Citation Graph (0, 0)][DBLP ] Conf ] Lifeng Wu NBTI/HCI Modeling and Full-Chip Analysis in Design Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Ohr Is Quality a Design Constraint for Sub 100nm Designs? [Citation Graph (0, 0)][DBLP ] Conf ] Platform Leadership in the Ambient Intelligence Era. [Citation Graph (0, 0)][DBLP ] Conf ] Quality SoC Design and Implementation for Real Manufacturability. [Citation Graph (0, 0)][DBLP ] Conf ] Quality Challenges of the Nanometer Design Realm. [Citation Graph (0, 0)][DBLP ] Conf ] Afshin Abdollahi , Farzan Fallah , Massoud Pedram Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains. [Citation Graph (0, 0)][DBLP ] Conf ] Geun Rae Cho , Tom Chen Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Rafik S. Guindi , Farid N. Najm Design Techniques for Gate-Leakage Reduction in CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bijan Alizadeh , Mohammad Reza Kakoee Using Integer Equations for High Level Formal Verification Property Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Gary Feierbach , Vijay Gupta True Coverage: A Goal of Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Gustavo Marrero Callicó , Antonio Núñez , Rafael Peset Llopis , Ramanathan Sethuraman Low-Cost and Real-Time Super-Resolution over a Video Encoder IP. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Pierre Heliot , Florent Parmentier , Marie-Pierre Baron LYS: A Solution for System on Chip (SoC) Production Cost and Time to Volume Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Koranne Solving the SoC Test Scheduling Problem Using Network Flow and Reconfigurable Wrappers. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Huang , Wu-Tung Cheng , Chien-Chung Tsai , Nilanjan Mukherjee , Sudhakar M. Reddy Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Chunsheng Liu , Krishnendu Chakrabarty Compact Dictionaries for Fault Diagnosis in BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-In Henry Chen , Kiran George Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] F. Duan , R. Castagnetti , R. Venkatraman , O. Kobozeva , S. Ramesh Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability. [Citation Graph (0, 0)][DBLP ] Conf ] Qi-De Qian , Sheldon X.-D. Tan Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Pradiptya Ghosh , Chung-shin Kang , Michael Sanie , David Pinto New DFM Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains. [Citation Graph (0, 0)][DBLP ] Conf ] M. C. Scott , M. O. Peralta , Jo Dale Carothers System and Framework for QA of Process Design Kits. [Citation Graph (0, 0)][DBLP ] Conf ] Gilles-Eric Descamps , Satish Bagalkotkar , Subramaniam Ganesan , Sridhar Subramaniam , Hem Hingarh The iFlow Design Factory: Evolving Chip Design from an Art to a Process, through Adaptive Resource Management, and Qualified Data Exchange. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Te Chuang , Rajiv V. Joshi , Ruchir Puri , Keunwoo Kim Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Won Namgoong , Jongrit Lerdworatawee Revisiting the Noise Figure Design Metric for Digital Communication Receiver. [Citation Graph (0, 0)][DBLP ] Conf ] N. S. Nagaraj , Tom Bonifield , Abha Singh , Frank Cano , Usha Narasimha , Mak Kulkarni , Poras T. Balsara , Cyrus Cantrell Benchmarks for Interconnect Parasitic Resistance and Capacitance. [Citation Graph (0, 0)][DBLP ] Conf ] Murat R. Becer , David Blaauw , Ilan Algor , Rajendran Panda , Chanhee Oh , Vladimir Zolotov , Ibrahim N. Hajj Post-Route Gate Sizing for Crosstalk Noise Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoliang Bai , Rajit Chandra , Sujit Dey , P. V. Srinivas Noise-Aware Driver Modeling for Nanometer Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Chen , Amjad Hajjar Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Kuan Tsai , Malgorzata Marek-Sadowska Modeling Crosstalk Induced Delay. [Citation Graph (0, 0)][DBLP ] Conf ] Hai Lan , Zhiping Yu , Robert W. Dutton A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Terry Blanchard Assessment of the OpenAccess Standard: Insights on the new EDA Industry Standard from Hewlett-Packard, a Beta Partner and Contributing Developer. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Igor L. Markov Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint. [Citation Graph (0, 0)][DBLP ] Conf ] D. R. Cottrell , T. J. Grebinski Interoperability Beyond Design: Sharing Knowledge between Design and Manufacturing. [Citation Graph (0, 0)][DBLP ] Conf ] Peter C. Salmon Advanced Module Packaging Method. [Citation Graph (0, 0)][DBLP ] Conf ] Michael X. Wang , Katsuharu Suzuki , Wayne Wei-Ming Dai Electrical and Thermal Analysis for System-in-a-Package (SiP) Implementation Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Wendemagegnehu T. Beyene , Chuck Yuan , Joong-Ho Kim , Madhavan Swaminathan Modeling and Analysis of Power Distribution Networks for Gigabit Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Dou Ker , Jeng-Jie Peng , Hsin-Chin Jiang Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC. [Citation Graph (0, 0)][DBLP ] Conf ] Addressing the IC Designer's Needs: Integrated Design Software for Faster, More Economical Chip Design. [Citation Graph (0, 0)][DBLP ] Conf ] Closing the Gap between ASIC and Full Custom: A Path to Quality Design. [Citation Graph (0, 0)][DBLP ] Conf ] A VLSI System Perspective for Microprocessors Beyond 90nm. [Citation Graph (0, 0)][DBLP ] Conf ] Soroush Abbaspour , Massoud Pedram , Payam Heydari Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers. [Citation Graph (0, 0)][DBLP ] Conf ] Hyung Gyu Lee , Sungyuep Nam , Naehyuck Chang Cycle-accurate Energy Measurement and High-Level Energy Characterization of FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Andrew B. Kahng Quantifying Error in Dynamic Power Estimation of CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Volkan Kursun , Siva Narendra , Vivek De , Eby G. Friedman Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Dongwoo Lee , Wesley Kwong , David Blaauw , Dennis Sylvester Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design. [Citation Graph (0, 0)][DBLP ] Conf ] Payam Heydari Design and Analysis of Low-Voltage Current-Mode Logic Buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Makram M. Mansour , Amit Mehrotra Reduced-Order Modeling Based on PRONY's and SHANK's Methods via the Bilinear Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Young-Jun Lee , Jong-Jin Lim , Yong-Bin Kim A Novel Clocking Strategy for Dynamic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Danica Stefanovic , Maher Kayal , Marc Pastre , Vanco B. Litovski Procedural Analog Design (PAD) Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Makram M. Mansour , Mohammad M. Mansour , Amit Mehrotra Parameterized Macrocells with Accurate Delay Models for Core-Based Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Wai-Ching Douglas Lam , Cheng-Kok Koh , Chung-Wen Albert Tsao Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Fu Hsiao , Malgorzata Marek-Sadowska , Sao-Jie Chen Minimizing Inter-Clock Coupling Jitter. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Andrew B. Kahng , Stefanus Mantik A Proposal for Routing-Based Timing-Driven Scan Chain Ordering. [Citation Graph (0, 0)][DBLP ] Conf ] Jae-Seok Yang , Jeong-Yeol Kim , Joon-Ho Choi , Moon-Hyun Yoo , Jeong-Taek Kong Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiyuki Shibuya , Rajeev Murgai , Tadashi Konno , Kazuhiro Emi , Kaoru Kawamura PDL: A New Physical Synthesis Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Colin C. McAndrew Statistical Modeling for Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Dou Ker , Hsin-Chyh Hsu , Jeng-Jie Peng Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chenggang Xu , Terri S. Fiez , Kartikeya Mayaram Coupled Simulation of Circuit and Piezoelectric Laminates. [Citation Graph (0, 0)][DBLP ] Conf ] Won-Seok Lee , Keun-Ho Lee , Jin-Kyu Park , Tae-Kyung Kim , Young-Kwan Park , Jeong-Taek Kong Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Chanhee Oh , David Blaauw , Murat R. Becer , Vladimir Zolotov , Rajendran Panda , Aurobindo Dasgupta Static Electromigration Analysis for Signal Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Tets Maniwa Hidden Quality, Crouching Customer - How Much Does the Quality of EDA Tools Impact Electronic Design? [Citation Graph (0, 0)][DBLP ] Conf ] S. Simon Wong , C. Patrick Yue , Richard Chang , So-Young Kim , Bendik Kleveland , Frank O'Mahony On-Chip Interconnect Inductance - Friend or Foe (Invited). [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Sato , Hiroo Masuda Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay. [Citation Graph (0, 0)][DBLP ] Conf ] Soyoung Kim , Yehia Massoud , S. Simon Wong On the Accuracy of Return Path Assumption for Loop Inductance Extraction for 0.1?m Technology and Beyond. [Citation Graph (0, 0)][DBLP ] Conf ] Payman Zarkesh-Ha , S. Lakshminarayann , Ken Doniger , William Loh , Peter Wright Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Li Yang , J. S. Yuan Analyzing Internal-Switching Induced Simultaneous Switching Noise. [Citation Graph (0, 0)][DBLP ] Conf ] Maria K. Michael , Spyros Tragoudas Generation of Hazard Identification Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Petros Drineas , Yiorgos Makris Concurrent Fault Detection in Random Combinational Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Daniela De Venuto , Michael J. Ohletz , Bruno Riccò Automatic Repositioning Technique for Digital Cell Based Window Comparators and Implementation within Mixed-Signal DfT Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Angela Krstic , Jing-Jia Liou , Kwang-Ting Cheng , Li-C. Wang On Structural vs. Functional Testing for Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Tsiatouhas , Th. Haniotakis , Angela Arapoyanni An Embedded IDDQ Testing Architecture and Technique. [Citation Graph (0, 0)][DBLP ] Conf ] 