Conferences in DBLP
Sreejit Chakravarty Supplemental Test Methods (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Geir Eide Design-for-Test Techniques for SoC Designs (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] J. Joseph Clement Electromigration Reliability Issues in High-Performance Circuit Design (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Charvaka Duvvury Issues in Deep Submicron State-of-the-Art ESD Design (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Shain Aur Hot Carrier Reliability and Design Considerations (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] John S. Suehle Ultra-thin Gate Oxide Reliability and Implications for Design (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Ersed Akcasu A General and Comparative Study of RC(0), RC, RCL and RCLK Modeling of Interconnects and Their Impact on the Design of Multi-Giga Hertz Processors (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Norman Chang Power/Ground Integrity Issues for Sub-130nm IC Designs (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Foty MOS Modeling, Design Quality, and Modern Analog Design (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Li-Fu Chang RLCK Extraction and Simulation in High-Speed SoC Designs (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Sumit Ghosh nVHDL: A Hardware Design Language for Modeling Discrete and Analog Design and Simulation of Mixed-Signal Electronic Systems (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Henry Chang Platform-Based Design: A Tutorial (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Coudert Optimization in an Integrated Physical Design Flow (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Marshall Quality Aspects of SOI Circuit Design (Tutorial Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Pallab K. Chatterjee , Richard Goering Evening Panel Discussion: Are the Interoperability Standards for EDA Too Little/Too Late for Real SoC Designs? [Citation Graph (0, 0)][DBLP ] Conf ] John Chilton IP REUSE QUALITY: "Intellectual Property" or "Intense Pain"? [Citation Graph (0, 0)][DBLP ] Conf ] Y. Lepejian Why Integrated Yield Management is a Necessity. [Citation Graph (0, 0)][DBLP ] Conf ] J. Kupec Design Success: Foundry Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Y. C. Pati What You Don't Know CAN Hurt You: Designing for Survival in a Sub-wavelength Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Reif , Andy Fan , Kuan-Neng Chen , Shamik Das Fabrication Technologies for Three-Dimensional Integrated Circuits (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Vikram Jandhyala , Yong Wang , Dipanjan Gope , C.-J. Richard Shi Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes. [Citation Graph (0, 0)][DBLP ] Conf ] Kaustav Banerjee , Amit Mehrotra Inductance Aware Interconnect Scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Gaofeng Wang , Xiaoning Qi , Zhiping Yu , Robert W. Dutton Accurate Model of Metal-Insulator-Semiconductor Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Himanshu Kaul , Dennis Sylvester Transition Aware Global Signaling (TAGS). [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Moritz Using the Open Library Architecture (OLA) Open Source API in Heterogeneous Design Flows (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Terry Blanchard , Rick Ferreri , Jim Wilmore The OpenAccess Coalition - The Drive to an Open Industry Standard Information Model, API, and Reference Implementation for IC Design Data (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Ralf Seepold , Natividad Martínez Madrid , Andreas Vörg , Wolfgang Rosenstiel , Martin Radetzki , P. Neumann , J. Haase A Qualification Platform for Design Reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Giora Ben-Yaacov , Pramod Suratkar , Marsha Holliday , Karen Bartleson Advancing Quality of EDA Software (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Aleksander Slusarczyk , Lech Józwiak Interoperability and Quality of New EDA Tools for Sequential Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Robert C. Aitken Test Generation and Fault Modeling for Stress Testing (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Y. Tsiatouhas , Th. Haniotakis , Dimitris Nikolos , Angela Arapoyanni Extending the Viability of IDDQ Testing in the Deep Submicron Era. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Koranne Design of Reconfigurable Access Wrappers for Embedded Core Based SoC Test. [Citation Graph (0, 0)][DBLP ] Conf ] Daniela De Venuto , Michael J. Ohletz , Bruno Riccò Testing of Analogue Circuits via (Standard) Digital Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Gianluca Cumani , Matteo Sonza Reorda , Giovanni Squillero Automatic Test Program Generation from RT-Level Microprocessor Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Enrico Malavasi , Stefano Zanella , Min Cao , Julian Uschersohn , Mike Misheloff , Carlo Guardiani Impact Analysis of Process Variability on Clock Skew. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Kocher , Gerhard Rappitsch Statistical Methods for the Determination of Process Corners. [Citation Graph (0, 0)][DBLP ] Conf ] Daegyu Lee , Jincheol Yoo , Kyusun Choi Design Method and Automation of Comparator Generation for Flash A/D Converter. [Citation Graph (0, 0)][DBLP ] Conf ] Chul-Hong Park , Soo-Han Choi , Sang-Uhk Rhie , Dong-Hyun Kim , Jun-Seong Park , Tae-Hwang Jang , Ji-Soong Park , Yoo-Hyon Kim , Moon-Hyun Yoo , Jeong-Taek Kong A Hybrid PPC Method Based on the Empirical Etch Model for the 0.14µm DRAM Generation and Beyond. [Citation Graph (0, 0)][DBLP ] Conf ] Prasun Raha , Scott Randall , Richard Jennings , Bob Helmick , Ajith Amerasekera , Baher Haroun A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. [Citation Graph (0, 0)][DBLP ] Conf ] Ting-Yuan Wang , Charlie Chung-Ping Chen Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Geng Bai , Ibrahim N. Hajj Simultaneous Switching Noise and Resonance Analysis of On-Chip Power Distribution Network. [Citation Graph (0, 0)][DBLP ] Conf ] Kenji Shimazaki , Shouzou Hirano , Hiroyuki Tsujikawa An EMI-Noise Analysis on LSI Design with Impedance Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Abby A. Ilumoka Chip Level Signal Integrity Analysis & Crosstalk Prediction Using Artificial Neural Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Wendemagegnehu T. Beyene , Chuck Yuan On the Use of Windows for Accurate Analysis of Package Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel N. Maynard Productivity Optimization Techniques for the Proactive Semiconductor Manufacturer (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Gary Smith A New Design Cost Model for the 2001 ITRS (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Martin Saint-Laurent , Vojin G. Oklobdzija , Simon S. Singh , Madhavan Swaminathan Optimal Sequencing Energy Allocation for CMOS Integrated Systems. [Citation Graph (0, 0)][DBLP ] Conf ] J. M. Gilbert , Ian M. Bell , D. R. Johnson Design, Manufacture and Test - Quality Test Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Stefanus Mantik Measurement of Inherent Noise in EDA Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Ron Wilson , Siva Narendra , Vivek De Evening Panel Discussion: Process Variation: Is It Too Much to Handle? [Citation Graph (0, 0)][DBLP ] Conf ] A. Raza The Role of ICs in the Creation of a Connected World and the Importance of Product Quality. [Citation Graph (0, 0)][DBLP ] Conf ] B. Brodersen Wireless Systems-on-a-Chip Design. [Citation Graph (0, 0)][DBLP ] Conf ] Chan Wu Microwave III-V Semiconductors for Telecommunications and Prospective of the III-V Industry. [Citation Graph (0, 0)][DBLP ] Conf ] Ulf Schlichtmann Tomorrows High-Quality SoCs Require High-Quality Embedded Memories Today. [Citation Graph (0, 0)][DBLP ] Conf ] Aiqun Cao , Naran Sirisantana , Cheng-Kok Koh , Kaushik Roy Synthesis of Selectively Clocked Skewed Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bok-Gue Park , Koon-Shik Cho , Jun Dong Cho Low Power VLSI Architecture of Viterbi Scorer for HMM-Based Isolated Word Recognition. [Citation Graph (0, 0)][DBLP ] Conf ] Dinesh Pamunuwa , Hannu Tenhunen On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Syed M. Alam , Donald E. Troxel , Carl V. Thompson A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zhuo Gao , Ji Luo , Hu Huang , Wei Zhang , Joseph B. Bernstein Reliable Laser Programmable Gate Array Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Bricaud VC Rating and Quality Metrics: Why Bother? [Citation Graph (0, 0)][DBLP ] Conf ] Emmanouil Kalligeros , Xrysovalantis Kavousianos , Dimitris Bakalis , Dimitris Nikolos An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Sule Ozev , Alex Orailoglu An Integrated Tool for Analog Test Generation and Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Gert Jervan , Zebo Peng , Raimund Ubar , Helena Kruus A Hybrid BIST Architecture and Its Optimization for SoC Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Kamalnayan Jayaraman , Vivekananda M. Vedula , Jacob A. Abraham Native Mode Functional Self-Test Generation for Systems-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Mandeep Singh , Israel Koren Incorporating Fault Tolerance in Analog-to-Digital Converters (ADCs). [Citation Graph (0, 0)][DBLP ] Conf ] Parag K. Lala , B. Kiran Kumar Human Immune System Inspired Architecture for Self-Healing Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Grégory Servel , Denis Deschacht , Françoise Saliou , Jean-Luc Mattei , Fabrice Huret Impact of Low-K on Crosstalk. [Citation Graph (0, 0)][DBLP ] Conf ] Amjad Hajjar , Tom Chen Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian Criteria. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit Ghosh In Search of the Origin of VHDL's Delta Delays. [Citation Graph (0, 0)][DBLP ] Conf ] Andrey V. Mezhiba , Eby G. Friedman Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Kyu Park , Keun-Ho Lee , Chang-Sub Lee , Gi-Young Yang , Young-Kwan Park , Jeong-Taek Kong Characterizing the Current Degradation of Abnormally Structured MOS Transistors Using a 3D Poisson Solver. [Citation Graph (0, 0)][DBLP ] Conf ] Tae-young Oh , Zhiping Yu , Robert W. Dutton AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical Corrections. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Dou Ker , Chien-Hui Chuang , Kuo-Chun Hsu , Wen-Yu Lo ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process. [Citation Graph (0, 0)][DBLP ] Conf ] Naoyuki Shigyo , Hirobumi Kawashima , Seiji Yasuda Design of ESD Protection Device Using Statistical Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Mehmet Sahinoglu , Scott Glover Economic Analysis of a Stopping-rule in Branch Coverage Testing. [Citation Graph (0, 0)][DBLP ] Conf ] David Scott , Shaoping Tang , Song Zhao , Mahalingam Nandakumar Device Physics Impact on Low Leakage, High Speed DSP Design Techniques (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Wai-Ching Douglas Lam , Cheng-Kok Koh , Chung-Wen Albert Tsao Power Supply Noise Suppression via Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Atul Maheshwari , Wayne Burleson , Russell Tessier Trading off Reliability and Power-Consumption in Ultra-low Power Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter A. Beerel Asynchronous Circuits: An Increasingly Practical Design Solution (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Resve A. Saleh , G. Lim , T. Kadowaki , K. Uchiyama Trends in Low Power Digital System-on-Chip Designs (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Shaz Qadeer , Serdar Tasiran Promising Directions in Hardware Design Verification (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Sébastien Pillement , Daniel Chillet , Olivier Sentieys Behavioral IP Specification and Integration Framework for High-Level Design Reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Sherief Reda , Rolf Drechsler , Alex Orailoglu On the Relation between SAT and BDDs for Equivalence Checking. [Citation Graph (0, 0)][DBLP ] Conf ] José R. Sendra , Javier del Pino , Antonio Hernández , Javier Hernández , Jaime Aguilera , Abdres Garcia-Alonso , Antonio Nunez Integrated Inductors Modeling and Tools for Automatic Selection and Layout Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Nguyen Quang Trung , Artur Kokoszka , Krystyna Siekierska , Adam Pawlak , Dariusz Obrebski , Norbert Lugowski Organization of a Microprocessor Design Process Using Internet-Based Interoperable Workflows. [Citation Graph (0, 0)][DBLP ] Conf ] Murat R. Becer , Rajendran Panda , David Blaauw , Ibrahim N. Hajj Pre-route Noise Estimation in Deep Submicron Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Emrah Acar , Sani R. Nassif , Ying Liu , Lawrence T. Pileggi Time-Domain Simulation of Variational Interconnect Models. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Zolotov , David Blaauw , Rajendran Panda , Chanhee Oh Noise Injection and Propagation in High Performance Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Lauren Hui Chen , Malgorzata Marek-Sadowska Efficient Closed-Form Crosstalk Delay Metrics. [Citation Graph (0, 0)][DBLP ] Conf ] Alexey Glebov , Sergey Gavrilov , David Blaauw , Vladimir Zolotov , Rajendran Panda , Chanhee Oh False-Noise Analysis Using Resolution Method. [Citation Graph (0, 0)][DBLP ] Conf ] Takayasu Sakurai Low-Power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Radu Marculescu , Diana Marculescu Does Q=MC2? (On the Relationship between Quality in Electronic Design and the Model of Colloidal Computing, invited). [Citation Graph (0, 0)][DBLP ] Conf ] Geun Rae Cho , Tom Chen Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Hung Lee , Yu-Chung Lin , Hsin-Hsiung Huang , Tsai-Ming Hsieh Structural Decomposition with Functional Considerations for Low Power. [Citation Graph (0, 0)][DBLP ] Conf ] Yazdan Aghaghiri , Farzan Fallah , Massoud Pedram ALBORZ: Address Level Bus Power Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Sunderland , Gary L. Duncan , Brad J. Rasmussen , Harry E. Nichols , Daniel T. Kain , Lawrence C. Lee , Brian A. Clebowicz , Richard W. Hollis IV , Larry Wissel , Tad Wilder Megagate ASICs for the Thuraya Satellite Digital Signal Processor (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Pin Su , Samel K. H. Fung , Weidong Liu , Chenming Hu Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD. [Citation Graph (0, 0)][DBLP ] Conf ] M. Leong , H.-S. Wong , E. Nowak , J. Kedzierski , E. Jones High Performance Double-Gate Device Technology Challenges and Opportunities (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Adrian M. Ionescu , V. Pott , R. Fritschi , Kaustav Banerjee , Michel J. Declercq , P. Renaud , C. Hibert , Philippe Flückiger , G. A. Racine Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Wasshuber Single-Electronics - How It Works. How It's Used. How It's Simulated (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Coudert Timing and Design Closure in Physical Design Flows (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Chee How Lim , W. Robert Daasch , George Cai A Thermal-Aware Superscalar Microprocessor (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Nicholas Chia-Yuan Chang , Yao-Wen Chang , Iris Hui-Ru Jiang Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Jin Dai , Michel Courtoy Hierarchical Front-End Physical Design Solution Drives Modified Hand-Off (invited). [Citation Graph (0, 0)][DBLP ] Conf ] Charlie Chung-Ping Chen , Ed Cheng Future SoC Design Challenges and Solutions (invited). [Citation Graph (0, 0)][DBLP ] Conf ] 