Conferences in DBLP
Rainer Leupers , Fabian David A Uniform Optimization Technique for Offset Assignment Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Luc De Coster , Marleen Adé , Rudy Lauwereins , J. A. Peperstraete Code Generation for Compiled Bit-True Simulation of DSP Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Kai Cheng , Youn-Long Lin Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Doris Keitel-Schulz , Norbert Wehn Issues in Embedded DRAM Development and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Chuck Siska A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Enrica Filippi , Luciano Lavagno , L. Licciardi , A. Montanaro , M. Paolini , Roberto Passerone , Marco Sgroi , Alberto L. Sangiovanni-Vincentelli Intellectual Property Re-use in Embedded System Co-design: An Industrial Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Vahid , Tony Givargis Incorporating Cores into System-Level Specification. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Leupers HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation. [Citation Graph (0, 0)][DBLP ] Conf ] Apostolos A. Kountouris , Christophe Wolinski False Path Analysis Based on a Hierarchical Control Representation. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Jäschke , Rainer Laur Resource Constrained Modulo Scheduling with Global Resource Sharing. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Tomiyama , Akihiko Inoue , Hiroto Yasuura Statistical Performance-Driven Module Binding in High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiana Bolchini , William Fornaciari , Fabio Salice , Donatella Sciuto Concurrent Error Detection at Architectural Level. [Citation Graph (0, 0)][DBLP ] Conf ] Yin-Tsung Hwang , Yuan-Hung Wang Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System. [Citation Graph (0, 0)][DBLP ] Conf ] Allan Rae , Sri Parameswaran Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-Evolution. [Citation Graph (0, 0)][DBLP ] Conf ] Francky Catthoor , Diederik Verkest , Erik Brockmeyer Proposal for Unified System Design Meta Flow in Task-Level and Instruction-Level Design Technology Research for Multi-Media Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Zhao Wu , Wayne Wolf Data-Path Synthesis of VLIW Video Signal Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Bringmann , Wolfgang Rosenstiel , Dirk Reichardt Synchronization Detection for Multi-Process Hierarchical Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Voigt Knudsen , Jan Madsen Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign. [Citation Graph (0, 0)][DBLP ] Conf ] Tony Givargis , Frank Vahid Interface Exploration for Reduced Power in Core-Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Takanori Okuma , Hiroyuki Tomiyama , Akihiko Inoue , Eko Fajar , Hiroto Yasuura Instruction Encoding Techniques for Area Minimization of Instruction ROM. [Citation Graph (0, 0)][DBLP ] Conf ] Ing-Jer Huang , Ping-Huei Xie Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Wonyong Sung , Junedong Kim , Soonhoi Ha Memory Efficient Software Synthesis from Dataflow Graph. [Citation Graph (0, 0)][DBLP ] Conf ] Karam S. Chatha , Ranga Vemuri A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Vahid A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes. [Citation Graph (0, 0)][DBLP ] Conf ] Soha Hassoun Fine Grain Incremental Rescheduling Via Architectural Retiming. [Citation Graph (0, 0)][DBLP ] Conf ] 