Conferences in DBLP
William P. Thurston The Challenge of Testing VLSI in the 1980's. [Citation Graph (0, 0)][DBLP ] Conf ] Kent Lunneborg A Unified Test Plan for LSI or VLSI Components. [Citation Graph (0, 0)][DBLP ] Conf ] Williams Ludwell Harrison , Robert P. Davidson , R. L. Wadsack BELLMACT-32 : A Testable 32 bit Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Bernard Courtois Analytical Testing of Data Processing Sections of Integrated CPUs. [Citation Graph (0, 0)][DBLP ] Conf ] Robert G. Dunn , A. Kwan , David P. Rodgers , D. Sandstrom , C. Sie System to Optimize Test Quality and Efficiency for Memories and LSI. [Citation Graph (0, 0)][DBLP ] Conf ] E. Kurzweil , L. Jambut Importance of Asynchronous Refreshing in Memory Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Winegarden , Donald Pannell Paragons for Memory Test. [Citation Graph (0, 0)][DBLP ] Conf ] Robert C. Evans Testing Repairable RAMs and Mostly Good Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Joan M. Morrissey , Ching-Hua Chow , Ronald C. Devries , C. Megivern An Approach to Memory Testing, Diagnostics and Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] G. K. Lukianoff , J. S. Wolcott , Joan M. Morrissey Electron-Beam Testing of VLSI Dyrnamic RAMs. [Citation Graph (0, 0)][DBLP ] Conf ] M. T. M. Segers A Self-Test Method for Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Arzoumanian , John A. Waicukauski Fault Diagnosis in an LSSD Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Chung Ho Chen Designing Testable Synchronous Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeru Takasaki , Masato Kawai , S. Funatsu , Akihiko Yamoda A Calculus of Testability Measure at the Functional Level. [Citation Graph (0, 0)][DBLP ] Conf ] Zeev Barzilai , Jacob Savir , George Markowsky , Merlin G. Smith VLSI Self-Testing Based on Syndrome Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Wilfried Daehn , Joachim Mucha Hardware Test Pattern Generation for Built-In Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Dave Peachey , Robert O'Harold An Enhanced Analog/Digital GPIB Based PCB Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Aldo Mastrocola In-Circuit Test Techniques Applied to Complex Digital Assemblies. [Citation Graph (0, 0)][DBLP ] Conf ] David K. Oka , Bradford Robbins , William Bowhers Automatic Testing of Speech Synthesis Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Charles Koehler A CCD Imager Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeru Sugamori , Kenji Yoshida , Hiromi Maruyama , Shinpei Kamata , Tsuneta Sudo Analysis and Definition of Overall Timing Accuracy in VLSI Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Chang , Ed Richards , David Richter The PIN Module: A High Accuracy Concept in Very High Frequency Pin Electronics. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Adams A Correlation Study of Modern Techniques Applied to the Testing of Telecommunication Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] John C. Lundy A Working Approach to Volume CODEC Testing. [Citation Graph (0, 0)][DBLP ] Conf ] R. A. Hum , D. L. Williams , J. W. Lamonde A High-Performance Integrated Analog/Digital Test and Characterization Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Franc Brglez Digital Signal Processing Considerations in Filter-Codec Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas W. Westcott The Self-Assist Test Approach to Embedded Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Dilip K. Bhavsar , Richard W. Heckelman Self-Testing by Polynomial Division. [Citation Graph (0, 0)][DBLP ] Conf ] Mark W. Levi CMOS Is Most Testable. [Citation Graph (0, 0)][DBLP ] Conf ] William R. Cook Internal Diagnostics for Tektronix Graphics Terminals. [Citation Graph (0, 0)][DBLP ] Conf ] Samuel Kitces , John E. Bauer Parametric Relationships for Self-Contained Test for Digital Avionics Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Kyushik Son , Dhiraj K. Pradhan Completely Self-Checking Checkers in PLAs. [Citation Graph (0, 0)][DBLP ] Conf ] Geoffrey J. Bunza Implications of Board Testing at Speed. [Citation Graph (0, 0)][DBLP ] Conf ] John J. Allard Dynamic Memory Array Card Burn-In and High Speed Functional Card Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Sacher High-Speed Functional Testing of Microprocessor-Based Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Jochan , Norman Landis , Duke Monson Computer-Guided Probing Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Robert B. Craven , E. Rachel Morris An 18-Bit Precision DC Measurement System. [Citation Graph (0, 0)][DBLP ] Conf ] T. Michael Souders , D. R. Flach An NBS Calibration Service for A/D and D/A Converters. [Citation Graph (0, 0)][DBLP ] Conf ] E. A. Sloane A System for Converter Testing Using Walsh Transform Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] J. Anson Whealler A New Technique for Testing Settling Time in a Production Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew V. Mahoney Automated Measurement of 12 to 16-Bit Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Kemon P. Taschioglou Applying Quality Curves for Economic Comparison of Alternative Test Strategies. [Citation Graph (0, 0)][DBLP ] Conf ] G. W. Jacob Preparation of Product Test Plans. [Citation Graph (0, 0)][DBLP ] Conf ] G. A. Perone , P. A. LaBerge The Economics of the Memory Tester Decision. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph A. Ruggieri Hidden Cost Considerations in Long Term Use of ATE Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Eugene R. Hnatek Documentation for Testability : The Supplier's Responsibility to the User. [Citation Graph (0, 0)][DBLP ] Conf ] Micahel R. Saleno Planning for Test of Custom IC Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Donald L. Wheater , Richard Soderman The Series/1 as a Test System Controller for System Verification and Calibration. [Citation Graph (0, 0)][DBLP ] Conf ] Robert S. Broughton Data Management for Large Memory Device Characterization. [Citation Graph (0, 0)][DBLP ] Conf ] R. N. Powell IBM's VLSI Logic Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Beau R. Wilson Jr. A Method for Testing Subnanosecond ECL. [Citation Graph (0, 0)][DBLP ] Conf ] Robert M. Rolfe High-Volume Production Testing and Its Impact on the Development of Microprocessor Prototyping Tools. [Citation Graph (0, 0)][DBLP ] Conf ] J. Thomas Zender Driving Forces Behind Field-Based System Testing. [Citation Graph (0, 0)][DBLP ] Conf ] John W. Marvill The IBM Maintenance Device. [Citation Graph (0, 0)][DBLP ] Conf ] Charles P. Frusterio Field System Test Strategies for the 1980's. [Citation Graph (0, 0)][DBLP ] Conf ] Gerald C. Goshaw DIAL : An Automated ATE Service Support System. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Chang Liaw , Stephen Y. H. Su , Yashwant K. Malaiya State Diagram Approach for Functional Testing of Control Section. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Y. H. Su , Yu-I Hsieh Testing Functional Faults in Digital Systems Described by Register Transfer Language. [Citation Graph (0, 0)][DBLP ] Conf ] James Y. O. Fong Microprocessor Modeling for Logic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob A. Abraham Functional Level Test Generation for Complex Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter S. Bottorff Functional Testing Folklore and Fact. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ancheta , J. C. Helland A Data Management System for Testing Memory Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Nalin Shah , Hira Ranga A Test Analysis Program for Memory Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Brad Snoulten , John Peacock ANGEL : Algorithmic Pattern Generation System. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur E. Downey A "Three Mode" Command Language for ATE. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce G. MacAloney Fault Spectrum: An Analysis of System Level Test with Proposed Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] William K. Jones Final Test of an LSI Populated System: A Pragmatic Approach. [Citation Graph (0, 0)][DBLP ] Conf ] D. C. Jessep Jr. Today a Collection of Modules: Tomorrow a System. [Citation Graph (0, 0)][DBLP ] Conf ] J. L. Saathoff Factory Final Test Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Predrag G. Kovijanic Single Testability Figure of Merit. [Citation Graph (0, 0)][DBLP ] Conf ] Kaoru Okazaki , Toshihiko Yahara Efficient Logic Verification and Test Validation for MOS LSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yacoub M. El-Ziq , Richard J. Cloutier Functional-Level Test Generation for Stuck-Open Faults in CMOS VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] R. L. Wadsack VLSI : How Much Fault Coverage Is Enough ? [Citation Graph (0, 0)][DBLP ] Conf ] R. W. Allen , C. D. Chen , M. M. Ervin-Willis , K. R. Rahlfs , R. F. Thulloss , S. L. Wu DORA : A System of CAD Post-Processors Providing Test Programs and Automatic Diagnostics Data for Digital Device and Board Manufacture. [Citation Graph (0, 0)][DBLP ] Conf ] M. Ray Mercer , Vishwani D. Agrawal , Carlos M. Roman Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] 