Conferences in DBLP
James T. Healy Future Management of the Semiconductor Manufacturing Process. [Citation Graph (0, 0)][DBLP ] Conf ] Colin Maunder Plug and Play or Plug and Pray: We Have a Right to Know It Will Work (Or Why It Won't). [Citation Graph (0, 0)][DBLP ] Conf ] Edward I. Cole Jr. , Jerry M. Soden , Paiboon Tangyunyong , Patrick L. Candelaria , Richard W. Beegle , Daniel L. Barton , Christopher L. Henderson , Charles F. Hawkins Transient Power Supply Voltage (VDDT ) Analysis for Detecting IC Defects. [Citation Graph (0, 0)][DBLP ] Conf ] J. S. Beasley , S. Pour-Mozafari , D. Huggett , Alan W. Righter , C. J. Apodaca iDD Pulse Response Testing Applied to Complex CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] James F. Plusquellic , Donald M. Chiarulli , Steven P. Levitan Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data. [Citation Graph (0, 0)][DBLP ] Conf ] Indradeep Ghosh , Niraj K. Jha , Sujit Dey A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Bahram Pouya , Nur A. Touba Modifying User-Defined Logic for Test Access to Embedded Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Lee Whetsel An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro J. Yamaguchi , Masahiro Ishida , Marco Tilgner , Dong Sam Ha An Efficient Method for Compressing Test Data. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Gage , Ben Brown , John Donaldson , Alexander Joffe Hardware Compression Speeds on Bitmap Fail Display. [Citation Graph (0, 0)][DBLP ] Conf ] David C. Keezer , R. J. Wenzel Low-Cost ATE PinElectronics for Multigigabit-per-Second At-Speed Test. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Flint A Simulation-Based JTAG ATPG Optimized for MCMs. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas G. Foote , Dale E. Hoffman , William V. Huott , Timothy J. Koprowski , Bryan J. Robbins , Mary P. Kusko Testing the 400-MHz IBM Generation-4 CMOS Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Otto A. Torreiter , Ulrich Baur , Georg Goecke , Kevin Melocco Testing the Enterprise IBM System/390TM Multi Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Ted T. Turner Capacitive Leadframe Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Chuck Robinson Analog AC Harmonic Method for Detecting Solder Opens. [Citation Graph (0, 0)][DBLP ] Conf ] Ralf Arnold , Markus Feuser , Horst-Udo Wedekind , Thorsten Bode Experiences with Implementation of IDDQ Test for Identification and Automotive Products. [Citation Graph (0, 0)][DBLP ] Conf ] Antoni Ferré , Joan Figueras IDDQ Characterization in Submicron CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Keshavarzi , Kaushik Roy , Charles F. Hawkins Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Anne E. Gattiker , Wojciech Maly Current Signatures: Application. [Citation Graph (0, 0)][DBLP ] Conf ] Harry Hulvershorn 1149.5: Now It's a Standard, So What? [Citation Graph (0, 0)][DBLP ] Conf ] Adam Cron IEEE P1149.4-Almost a Standard. [Citation Graph (0, 0)][DBLP ] Conf ] Bozena Kaminska , Karim Arabi , I. Bell , José L. Huertas , B. Kim , Adoración Rueda , Mani Soma , Prashant Goteti Analog and Mixed-Signal Benchmark Circuits-First Release. [Citation Graph (0, 0)][DBLP ] Conf ] Yervant Zorian Test Requirements for Embedded Core-Based Systems and IEEE P1500. [Citation Graph (0, 0)][DBLP ] Conf ] Theo J. Powell , Dan Cline , Francis Hii A 256Meg SDRAM BIST for Disturb Test Application. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg E. Vollrath Cell Signal Measurement for High-Density DRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] R. Dean Adams , Edmond S. Cooley , Patrick R. Hansen A Self-Test Circuit for Evaluating Memory Sense-Amplifier Signal. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. van de Goor , Mike Lin The Implementation of Pseudo-Random Memory Tests on Commercial Memory Testers. [Citation Graph (0, 0)][DBLP ] Conf ] Kelly A. Ockunzzi , Christos A. Papachristou Testability Enhancement for Behavioral Descriptions Containing Conditional Statements. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Chickermane , Kamran Zarrineh Addressing Early Design-For-Test Synthesis in a Production Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Harbinder Singh , James Beausang , Girish Patankar A Symbolic Simulation-Based ANSI/IEEE Std 1149.1 Compliance Checker and BSDL Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiharu Asaka , Masaaki Yoshida , Subhrajit Bhattacharya , Sujit Dey H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs. [Citation Graph (0, 0)][DBLP ] Conf ] B. Karen McElfresh RF Introduction and Analog Junction Techniques for Finding Opens. [Citation Graph (0, 0)][DBLP ] Conf ] Stig Oresjo Unpowered Opens Test with X-Ray Laminography. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas W. Raymond Finding Opens with Optics. [Citation Graph (0, 0)][DBLP ] Conf ] Carol Stolicny , Richard Davies , Pamela McKernan , Tuyen Truong Manufacturing Pattern Development for the Alpha 21164 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Brauch , Jay Fleischman Design of Cache Test Hardware on the HP PA8500. [Citation Graph (0, 0)][DBLP ] Conf ] Adrian Carbine , Derek Feltham Pentium® Pro Processor Design for Test and Debug. [Citation Graph (0, 0)][DBLP ] Conf ] Yeoh Eng Hong , Martin Tay Tiong We The Application of Novel Failure Analysis Techniques for Advanced Multi-Layered CMOS Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher L. Henderson , Jerry M. Soden Signature Analysis for IC Diagnosis and Failure Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Phil Nigh , Donato Forlenza , Franco Motika Application and Analysis of IDDQ Diagnostic Software. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnendu Chakrabarty , Jian Liu , Minyao Zhu , Brian T. Murray Test Width Compression for Built-In Self Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Fagot , Patrick Girard , Christian Landrault On Using Machine Learning for Logic BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Gundolf Kiefer , Hans-Joachim Wunderlich Using BIST Control for Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Von-Kyoung Kim , Tom Chen , Mick Tegethoff ASIC Manufacturing Test Cost Prediction at Early Design Stage. [Citation Graph (0, 0)][DBLP ] Conf ] Adit D. Singh , Phil Nigh , C. Mani Krishna Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study. [Citation Graph (0, 0)][DBLP ] Conf ] K. E. Newman , David C. Keezer A Low-Cost Massively-Parallel Interconnect Test Method for MCM Substrates. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro J. Yamaguchi , Mani Soma Dynamic Testing of ADCs Using Wavelet Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen K. Sunter , Naveena Nagi A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Benoit Dufort , Gordon W. Roberts Signal Generation Using Periodic Single-and Multi-Bit Sigma-Delta Modulated Streams. [Citation Graph (0, 0)][DBLP ] Conf ] R. Scott Fetherston , Imtiaz P. Shaik , Siyad C. Ma Testability Features of AMD-K6TM Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Carol Pyron , Javier Prado , James Golab Next-Generation PowerPCTM Microprocessor Test Strategy Improvements. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Mateja , Alfred L. Crouch , Renny Eisele , Grady Giles , Dale Amason A Case Study of the Test Development for the 2nd Generation ColdFire® Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] W. Kent Fuchs Logic Diagnosis-Diversion or Necessity? [Citation Graph (0, 0)][DBLP ] Conf ] Paul G. Ryan Logical Diagnosis Solutions Must Drive Yield Improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry M. Soden , Christopher L. Henderson IC Diagnosis: Industry Issues. [Citation Graph (0, 0)][DBLP ] Conf ] Angela Krstic , Kwang-Ting Cheng , Srimat T. Chakradhar Design for Primitive Delay Fault Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir Scan Latch Design for Delay Test. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh C. Tekumalla , Premachandran R. Menon Delay Testing with Clock Control: An Alternative to Enhanced Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Osama K. Abu-Shahla , Ian M. Bell An On-Line Self-Testing Switched-Current Integrator. [Citation Graph (0, 0)][DBLP ] Conf ] A. L. Burress , Parag K. Lala On-Line Testable Logic Desgin for FPGA Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Charles E. Stroud , M. Ding , S. Seshadri , Ramesh Karri , I. Kim , S. Roy , S. Wu A Parameterized VHDL Library for On-Line Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth P. Parker , John E. McDermid , Rodney A. Browen , Kozo Nuriya , Katsuhiro Hirayama , Akira Matsuzawa Design, Fabrications and Use of Mixed-Signal IC Testability Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Chauchin Su , Yue-Tsang Chen , Shyh-Jye Jou Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. [Citation Graph (0, 0)][DBLP ] Conf ] José Machado da Silva , Ana C. Leão , José Silva Matos , José Carlos Alves Implementation of Mixed Current/Voltage Testing Using the IEEE P1149.4 Infrastructure. [Citation Graph (0, 0)][DBLP ] Conf ] James J. Brandes High-Performance Production Test Contractors for Fine-Pitch Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nicholas Sporck A New Probe Card Technology Using Compliant MicrospringsTM . [Citation Graph (0, 0)][DBLP ] Conf ] R. Dennis Bates The Search for the Universal Probe Card Solution. [Citation Graph (0, 0)][DBLP ] Conf ] Charles E. Stroud , Eric Lee , Miron Abramovici BIST-Based Diagnostics of FPGA Logic Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Kun-Han Tsai , Malgorzata Marek-Sadowska , Janusz Rajski Scan-Encoded Test Pattern Generation for BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Sichao Wei , Pranab K. Nag , Ronald D. Blanton , Anne E. Gattiker , Wojciech Maly To DFT or Not to DFT? [Citation Graph (0, 0)][DBLP ] Conf ] Eberhard Böhl , Thomas Lindenkreuz , R. Stephan The Fail-Stop Controller AE11. [Citation Graph (0, 0)][DBLP ] Conf ] Karim Arabi , Bozena Kaminska Design and Realization of an Accurate Built-In Current Sensor for On-Line Power Dissipation Measurement and IDDQ Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , Michele Favalli , Bruno Riccò On-Line Testing Scheme for Clock's Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Haluk Konuk , F. Joel Ferguson Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , Yves Bertrand Test Strategy Sensitivity to Defect Parameters. [Citation Graph (0, 0)][DBLP ] Conf ] Gilbert Vandling , Thomas Bartenstein Fault Model Extension for Diagnosing Custom Cell Fails. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen K. Sunter P1149.4-Problem or Solution for Mixed-Signal IC Design? [Citation Graph (0, 0)][DBLP ] Conf ] Mathieu Gagnon , Bozena Kaminska Optical Communication Channel Test Using BIST Approaches. [Citation Graph (0, 0)][DBLP ] Conf ] William J. Hughes III System-Level Boundary-Scan in a Highly Integrated Switch. [Citation Graph (0, 0)][DBLP ] Conf ] Jiun-Lang Huang , Kwang-Ting Cheng Analog Fault Diagnosis for Unpowered Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Bret A. Stewart Board Level Automated Fault Injection for Fault Coverage and Diagnostic Efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Robert E. Huston Pin Margin Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Westfall Memory Test-Debugging Test Vectors Without ATE. [Citation Graph (0, 0)][DBLP ] Conf ] Lakshmikantha S. Prabhu , Daniel A. Rosenthal A DSP-Based Feedback Loop for Mixed-Signal VLSI Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Yuhai Ma , Wanchun Shi OLDEVDTP: A Novel Environment for Off-Line Debugging of VLSI Device Test Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Richard McGowen , F. Joel Ferguson Incorporating Physical Design-for-Test into Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Nilanjan Mukherjee , Janusz Rajski , Jerzy Tyszer Parameterizable Testing Scheme for FIR Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Sridhar Narayanan , Ashutosh Das An Efficient Scheme to Diagnose Scan Chains. [Citation Graph (0, 0)][DBLP ] Conf ] Subhasish Mitra , LaNae J. Avra , Edward J. McCluskey Scan Synthesis for One-Hot Signals. [Citation Graph (0, 0)][DBLP ] Conf ] Elizabeth M. Rudnick , Janak H. Patel Putting the Squeeze on Test Sequences. [Citation Graph (0, 0)][DBLP ] Conf ] M. H. Konijnenburg , J. Th. van der Linden , A. J. van de Goor Sequential Test Generation with Advanced Illegal State Search. [Citation Graph (0, 0)][DBLP ] Conf ] Raghuram S. Tupuri , Jacob A. Abraham A Novel Functional Test Generation Method for Processors Using Commercial ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Paolo Prinetto , Matteo Sonza Reorda Testability Analysis and ATPG on Behavioral RT-Level VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Arnold Frisch , Thomas Almy HABIST: Histogram-Based Analog Built-In Self-Test. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas M. Bocek , Tuyen D. Vu , Mani Soma , Jason D. Moffatt Experimental Results for Current-Based Analog Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Benoît R. Veillette , Gordon W. Roberts On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Karim Arabi , Bozena Kaminska Oscillation Built-In Self Test (OBIST) Scheme for Functional and Structural Testing of Analog and Mixed-Signal Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bob Cometta , Jan Witte Low Current and Low Voltages-The High-End OP AMP Testing Challenge. [Citation Graph (0, 0)][DBLP ] Conf ] Minh Quach , Kim Harper Real-Time In-situ Monitoring and Characterization of Production Wafer Probing Process. [Citation Graph (0, 0)][DBLP ] Conf ] Weiyu Chen , Melvin A. Breuer , Sandeep K. Gupta Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh Raina , Charles Njinda , Robert F. Molyneaux How Seriously Do You Take Your Possible-Detect Faults? [Citation Graph (0, 0)][DBLP ] Conf ] Ajay Khoche , Erik Brunvand ACT: A DFT Tool for Self-Timed Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] James P. Cusey , Janak H. Patel BART: A Bridging Fault Test Generation for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Seongmoon Wang , Sandeep K. Gupta DS-LFSR: A New BIST TPG for Low Heat Dissipation. [Citation Graph (0, 0)][DBLP ] Conf ] J. Li , X. Sun , K. Soon Tree-Structured Linear Cellular Automata and Their Applications as PRPGs. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitris Gizopoulos , Antonis M. Paschalis , Yervant Zorian , Mihalis Psarakis An Effective BIST Scheme for Arithmetic Logic Units. [Citation Graph (0, 0)][DBLP ] Conf ] Srikanth Venkataraman , W. Kent Fuchs Diagnosis of Bridging Faults in Sequential Circuits Using Adaptive Simulation, State Storage, and Path-Tracing. [Citation Graph (0, 0)][DBLP ] Conf ] David B. Lavo , Tracy Larrabee , F. Joel Ferguson , Brian Chess , Jayashree Saxena , Kenneth M. Butler Bridging Fault Diagnosis in the Absence of Physical Information. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Rajski , Jerzy Tyszer Fault Diagnosis in Scan-Based BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Ramakrishna Voorakaranam , Sudip Chakrabarti , Junwei Hou , Alfred V. Gomes , Sasikumar Cherubal , Abhijit Chatterjee , William H. Kao Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Chen-Yang Pan , Kwang-Ting Cheng Fault Macromodeling for Analog/Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijeet Kolpekwar , Ronald D. Blanton Development of a MEMS Testing Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Mitch Aigner Embedded At-Speed Test Probe. [Citation Graph (0, 0)][DBLP ] Conf ] Yukiya Miura An IDDQ Sensor Circuit for Low-Voltage ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Tony Savor , Rudolph E. Seviora Supervisors for Testing Non-Deterministically Specified Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Li-C. Wang , Magdy S. Abadir A New Validation Methodology Combining Test and Formal Verification for PowerPCTM Microprocessor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Raimi , James Lear Analyzing a PowerPCTM 620 Microprocessor Silicon Failure Using Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Shi-Yu Huang , Kwang-Ting Cheng , Kuang-Chien Chen , David Ihsin Cheng Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Soumitra Bose , Vishwani D. Agrawal , Thomas G. Szymanski Algorithms for Switch Level Delay Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Zhongcheng Li , Robert K. Brayton , Yinghua Min Efficient Identification of Non-Robustly Untestable Path Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Tapan J. Chakraborty , Vishwani D. Agrawal Effective Path Selection for Delay Fault Testing of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory A. Maston Structuring STIL for Incremental Test Development. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wohl , John A. Waicukauski A Unified Interface for Scan Test Generation Based on STIL. [Citation Graph (0, 0)][DBLP ] Conf ] John W. Sheppard , Leslie A. Orlidge Artificial Intelligence Exchange and Service Tie to All Test Environments (AI-ESTATE)-A New Standard for System Diagnostics. [Citation Graph (0, 0)][DBLP ] Conf ] Dave Unzicker , Michael Bonham , Rey Rincon Advances in Probe Technology: Best Sessions of the'97 Southwest Test Workshop. [Citation Graph (0, 0)][DBLP ] Conf ] Steven F. Oakland Why Would an ASIC Foundry Accept Anything Less than Full Scan? [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Rearick The Case of Partial Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas W. Raymond , Dominic F. Haigh Why Automate Optical Inspection? [Citation Graph (0, 0)][DBLP ] Conf ] William R. Simpson Ethics, Professionalism and Accountability in Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Pye Vision Inspection: Meeting the Promise? [Citation Graph (0, 0)][DBLP ] Conf ] Donald Burr Solder Paste Inspection: Process Control for Defect Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Phil Nigh , Wayne M. Needham , Kenneth M. Butler , Peter C. Maxwell , Robert C. Aitken , Wojciech Maly So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas L. Anderson Thoughts on Core Integration and Test. [Citation Graph (0, 0)][DBLP ] Conf ] Rudy Garcia Embedded Core Test Plug-n-Play: Is It Achievable? [Citation Graph (0, 0)][DBLP ] Conf ] Lee Whetsel Test Access of TAP'ed & Non-TAP'ed Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Nicolaidis On-Line Testing for VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Anne Meixner , Jash Banik Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique. [Citation Graph (0, 0)][DBLP ] Conf ] 