Conferences in DBLP
Technical Program Committee. [Citation Graph (0, 0)][DBLP ] Conf ] Technical Paper Reviewers. [Citation Graph (0, 0)][DBLP ] Conf ] International Test Conference - Copyright. [Citation Graph (0, 0)][DBLP ] Conf ] TTTC: Test Technology Technical Council. [Citation Graph (0, 0)][DBLP ] Conf ] Welcoming Message. [Citation Graph (0, 0)][DBLP ] Conf ] Steering Committee and Subcommittees. [Citation Graph (0, 0)][DBLP ] Conf ] Ned Kornfield Memorial. [Citation Graph (0, 0)][DBLP ] Conf ] International Test Conference - Cover. [Citation Graph (0, 0)][DBLP ] Conf ] 2003 Paper Awards. [Citation Graph (0, 0)][DBLP ] Conf ] 2005 Call for Papers. [Citation Graph (0, 0)][DBLP ] Conf ] ITC Technical Paper Evaluation and Selection Process. [Citation Graph (0, 0)][DBLP ] Conf ] International Test Conference - Title Page. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Koenemann Test In the Era of "What You see Is NOT What You Get". [Citation Graph (0, 0)][DBLP ] Conf ] Robert Madge New Test Paradigms for Yield and Manufacturability. [Citation Graph (0, 0)][DBLP ] Conf ] Benoit Provost , Chee How Lim , Mo Bashir , Ali Muhtaroglu , Tiffany Huang , Kathy Tian , Mubeen Atha , Cangsang Zhao , Harry Muljono AC IO Loopback Design for High Speed µProcessor IO Test. [Citation Graph (0, 0)][DBLP ] Conf ] Jing Zeng , Magdy S. Abadir , A. Kolhatkar , G. Vandling , Li-C. Wang , Jacob A. Abraham On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Wu , Mike Lin , Madhukar Reddy , Talal Jaber , Anil Sabbavarapu , Larry Thatcher An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Valentin Gherman , Hans-Joachim Wunderlich , Harald P. E. Vranken , Friedrich Hapke , Michael Wittke , Michael Garbers Efficient Pattern Mapping for Deterministic Logic BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Liyang Lai , Janak H. Patel , Thomas Rinderknecht , Wu-Tung Cheng Logic BIST with Scan Chain Segmentation. [Citation Graph (0, 0)][DBLP ] Conf ] Omar I. Khan , Michael L. Bushnell Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro J. Yamaguchi , Masahiro Ishida , Kiyotaka Ichiyama , Mani Soma , Christian Krawinkel , Katsuaki Ohsawa , Masao Sugai A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Karen Taylor , Bryan Nelson , Alan Chong , Hieu Nguyen , Henry C. Lin , Mani Soma , Hosam Haggag , Jeff Huard , Jim Braatz Experimental Results for High-Speed Jitter Measurement Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen K. Sunter , Aubin Roy , Jean-Francois Cote An Automated, Complete, Structural Test Solution for SERDES. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin M. Mauck , Vishnumohan Ravichandran , Usman Azeez Mughal A Design for Test Technique for Parametric Analysis of SRAM: On-Die Low Yield Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. van de Goor , Said Hamdioui , Rob Wadsworth Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Lung Su , Rei-Fu Huang , Cheng-Wen Wu , Chien-Chung Hung , Ming-Jer Kao , Yeong-Jar Chang , Wen Ching Wu MRAM Defect Analysis and Fault Modeli. [Citation Graph (0, 0)][DBLP ] Conf ] Stas Polonsky , Keith A. Jenkins , Alan J. Weger , Shinho Cho CMOS IC diagnostics using the luminescence of OFF-state leakage currents. [Citation Graph (0, 0)][DBLP ] Conf ] Peilin Song , Franco Stellari , Alan J. Weger , Tian Xia A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Reddy , John Carulli , Anand T. Krishnan , William Bosch , Brendan Burgess Impact of Negative Bias Temperature Instability on Product Parametric Drift. [Citation Graph (0, 0)][DBLP ] Conf ] Heon C. Kim , Hong Shin Jun , Xinli Gu , Sung Soo Chung At-Speed Interconnect Test and Diagnosis of External Memories on a System. [Citation Graph (0, 0)][DBLP ] Conf ] Kendrick Baker , Mehrdad Nourani Interconnect Test Pattern Generation Algorithm For Meeting Device and Global SSO Limits With Safe Initial Vectors. [Citation Graph (0, 0)][DBLP ] Conf ] Hong Shin Jun , Sung Soo Chung , Sang H. Baeg Removing JTAG Bottlenecks in System Interconnect Test. [Citation Graph (0, 0)][DBLP ] Conf ] Manu Rehani , David Abercrombie , Robert Madge , Jim Teisher , Jason Saw ATE Data Collection - A comprehensive requirements proposal to maximize ROI of test. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan Hops , Brian Swing , Brian Phelps , Bruce Sudweeks , John Pane , James Kinslow Non-Deterministic DUT Behavior During Functional Testing of High Speed Serial Busses: Challenges and Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Patten Divide and Conquer based Fast Shmoo algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Madge , Brady Benware , Ritesh P. Turakhia , W. Robert Daasch , Chris Schuermyer , Jens Ruffler In Search of the Optimum Test Set - Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost. [Citation Graph (0, 0)][DBLP ] Conf ] Bram Kruseman , Ananta K. Majhi , Guido Gronthoud , Stefan Eichenberger On Hazard-free Patterns for Fine-delay Fault Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Wangqi Qiu , Jing Wang , D. M. H. Walker , Divya Reddy , Zhuo Li , Weiping Shi , Hari Balachandran K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Saravanan Padmanaban , Spyros Tragoudas A Critical Path Selection Method for Delay Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Haihua Yan , Adit D. Singh Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study. [Citation Graph (0, 0)][DBLP ] Conf ] Ashwin Raghunathan , Ji Hwan (Paul) Chun , Jacob A. Abraham , Abhijit Chatterjee Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters. [Citation Graph (0, 0)][DBLP ] Conf ] Abhishek Singh , Chintan Patel , Jim Plusquellic On-Chip Impulse Response Generation for Analog and Mixed-Signal Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Foster F. Dai , Charles E. Stroud , Dayu Yang , Shuying Qi Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer. [Citation Graph (0, 0)][DBLP ] Conf ] Geert Seuren , Tom Waayers Extending the Digital Core-based Test Methodology to Support Mixed-Signal. [Citation Graph (0, 0)][DBLP ] Conf ] Bram Kruseman , Ananta K. Majhi , Camelia Hora , Stefan Eichenberger , Johan Meirlevede Systematic Defects in Deep Sub-Micron Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Schuermyer , Jens Ruffler , W. Robert Daasch Minimum Testing Requirements to Screen Temperature Dependent Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Phil Nigh , Anne E. Gattiker Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions. [Citation Graph (0, 0)][DBLP ] Conf ] Chintan Patel , Abhishek Singh , Jim Plusquellic Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew L. King , Kewal K. Saluja Testing Micropipelined Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Yang , Kaijie Wu , Ramesh Karri Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar , Graham Hetherington A Holistic Parallel and Hierarchical Approach towards Design-For-Test. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth M. Butler , Jayashree Saxena , Tony Fryars , Graham Hetherington Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth P. Parker A New Probing Technique for High-Speed/High-Density Printed Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Rodger Schuttert , D. C. L. van Geest , A. Kumar On-Chip Mixed-Signal Test Structures Re-used for Board Test. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Michel , Rosa D. Reinosa Test Strategy Cost Model Innovations. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Verma , Charles Robinson , Steve Butkovich Production Test Effectiveness of Combined Automated Inspection and ICT Test Strategies. [Citation Graph (0, 0)][DBLP ] Conf ] Rochit Rajsuman , Masuda Noriyuki Open Architecture Test System: System Architecture and Design. [Citation Graph (0, 0)][DBLP ] Conf ] Ankan K. Pramanick , Ramachandran Krishnaswamy , Mark Elston , Toshiaki Adachi , Harsanjeet Singh , Bruce R. Parnas Test Programming Environment in a Modular, Open Architecture Test System. [Citation Graph (0, 0)][DBLP ] Conf ] David Dowding , Ernie Wahl , Don Organ Extending STIL 1450 Standard for Test Program Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Subhasish Mitra , Steven S. Lumetta , Michael Mitzenmacher X-Tolerant Signature Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Yuyi Tang , Hans-Joachim Wunderlich , Harald P. E. Vranken , Friedrich Hapke , Michael Wittke , Piet Engelke , Ilia Polian , Bernd Becker X-Masking During Logic BIST and Its Impact on Defect Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Chickermane , Brian Foutz , Brion L. Keller Channel Masking Synthesis for Efficient On-Chip Test Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Jason G. Brown , R. D. (Shawn) Blanton CAEN-BIST: Testing the NanoFabric. [Citation Graph (0, 0)][DBLP ] Conf ] Wenjing Rao , Alex Orailoglu , Ramesh Karri Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jing Huang , Mehdi Baradaran Tahoori , Fabrizio Lombardi Routability and Fault Tolerance of FPGA Interconnect Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Srikanth Venkataraman , Sudhakar M. Reddy Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Grzegorz Mrugalski , Chen Wang , Artur Pogiel , Jerzy Tyszer , Janusz Rajski Fault Diagnosis in Designs with Convolutional Compactors. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas J. Vogels , Thomas Zanon , Rao Desineni , R. D. (Shawn) Blanton , Wojciech Maly , Jason G. Brown , Jeffrey E. Nelson , Y. Fei , X. Huang , Padmini Gopalakrishnan , Mahim Mishra , V. Rovner , S. Tiwary Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. [Citation Graph (0, 0)][DBLP ] Conf ] Brion L. Keller , Mick Tegethoff , Thomas Bartenstein , Vivek Chickermane An Economic Analysis and ROI Model for Nanometer Test. [Citation Graph (0, 0)][DBLP ] Conf ] Xinli Gu , Cyndee Wang , Abby Lee , Bill Eklow , Kun-Han Tsai , Jan Arild Tofte , Mark Kassab , Janusz Rajski Realizing High Test Quality Goals with Smart Test Resource Usage. [Citation Graph (0, 0)][DBLP ] Conf ] Pamela S. Gillis , Francis Woytowich , Andrew Ferko , Kevin McCauley Low Overhead Delay Testing of ASICS. [Citation Graph (0, 0)][DBLP ] Conf ] Saghir A. Shaikh IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver. [Citation Graph (0, 0)][DBLP ] Conf ] Juha Häkkinen , Pekka Syri , Juha-Veikko Voutilainen , Markku Moilanen A Frequency Mixing and Sub-Sampling Based RF-Measurement Apparatus for IEEE 1149.4. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Rearick , Sylvia Patterson , Krista Dorner Integrating Boundary Scan into Multi-GHz I/O Circuitry. [Citation Graph (0, 0)][DBLP ] Conf ] Masashi Shimanouchi Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATE. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed Rashid Syed Automatic Delay Calibration Method for Multi-channel CMOS Formatter. [Citation Graph (0, 0)][DBLP ] Conf ] A. T. Sivaram , Pascal Pierra , Shida Sheibani , Nancy Wang-Lee , Jorge E. Solorzano , Lily Tran Active Tester Interface Unit Design For Data Collection. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Shi , Yiorgos Makris SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kameshwar Chandrasekar , Michael S. Hsiao Decision Selection and Learning for an All-Solutions ATPG Engine. [Citation Graph (0, 0)][DBLP ] Conf ] Junwu Zhang , Michael L. Bushnell , Vishwani D. Agrawal On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Dave Mark , Jenny Fan Localizing Open Interconnect Defects using Targeted Routing in FPGA's. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi Baradaran Tahoori , Subhasish Mitra Interconnect Delay Testing of Designs on Programmable Logic Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi Baradaran Tahoori Application-Dependent Diagnosis of FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] A. Cabbibo , J. Conder , M. Jacobs Feed Forward Test Methodology Utilizing Device Identification. [Citation Graph (0, 0)][DBLP ] Conf ] Leendert M. Huisman , Maroun Kassab , Leah Pastel Data Mining Integrated Circuit Fails with Fail Commonalities. [Citation Graph (0, 0)][DBLP ] Conf ] M. Enamul Amyeen , Srikanth Venkataraman , Ajay Ojha , Sangbong Lee Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Sandip Kundu , T. M. Mak , Rajesh Galivanche Trends in manufacturing test methods and their implications. [Citation Graph (0, 0)][DBLP ] Conf ] Bart Vermeulen , Camelia Hora , Bram Kruseman , Erik Jan Marinissen , Robert Van Rijsinge Trends in Testing Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Alfred L. Crouch Future Trends in Test: The Adoption and Use of Low Cost Structural Testers. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Eklow , Anoosh Hosseini , Chi Khuong , Shyam Pullela , Toai Vo , Hien Chau Simulation Based System Level Fault Insertion Using Co-verification Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Chen-Huan Chiang , Paul J. Wheatley , Kenneth Y. Ho , Ken L. Cheung Testing and Remote Field Update of Distributed Base Stations in a Wireless Network. [Citation Graph (0, 0)][DBLP ] Conf ] Yujun Zhang , Zhongcheng Li IPV6 Conformance Testing: Theory and Practice. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Hafed , Antonio H. Chan , Geoffrey Duerden , Bardia Pishdad , Clarence Tam , Sebastien Laberge , Gordon W. Roberts A High-Throughput 5 GBps Timing and Jitter Test Module Featuring Localized Processing. [Citation Graph (0, 0)][DBLP ] Conf ] A. T. Sivaram , Masashi Shimanouchi , Howard Maassen , Robert Jackson Tester Architecture For The Source Synchronous Bus. [Citation Graph (0, 0)][DBLP ] Conf ] David C. Keezer , Dany Minier , F. Binette Modular Extension of ATE to 5 Gbps. [Citation Graph (0, 0)][DBLP ] Conf ] Hans T. Heineken , Jitendra Khare Test Strategies For a 40Gbps Framer SoC. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Laquai A Model-based Test Approach for Testing High-Speed PLLs and Phase Regulation Circuitry in SOC Devices. [Citation Graph (0, 0)][DBLP ] Conf ] K. Nikila , Rubin A. Parekhji DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device. [Citation Graph (0, 0)][DBLP ] Conf ] Erkan Acar , Sule Ozev Delayed-RF Based Test Development for FM Transceivers Using Signature Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Dana Brown , John Ferrario , Randy Wolf , Jing Li , Jayendra Bhagat RF Testing on a Mixed Signal Tester. [Citation Graph (0, 0)][DBLP ] Conf ] Soumendu Bhattacharya , Abhijit Chatterjee Use of Embedded Sensors for Built-In-Test of RF Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Alper Sen , Vijay K. Garg , Jacob A. Abraham , Jayanta Bhadra Formal Verification of a System-on-Chip Using Computation Slicing. [Citation Graph (0, 0)][DBLP ] Conf ] Qingwei Wu , Michael S. Hsiao State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Geeng-Wei Lee , Juinn-Dar Huang , Jing-Yang Jou , Chun-Yao Wang Verification on Port Connections. [Citation Graph (0, 0)][DBLP ] Conf ] Charles E. Stroud , John Sunwoo , Srinivas M. Garimella , Jonathan Harris Built-In Self-Test for System-on-Chip: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Remmers , Moe Villalba , Richard Fisette Hierarchical DFT Methodology - A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] C. J. Clark , Mike Ricchetti A Code-less BIST Processor for Embedded Test and in-system configuration of Boards and Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Liviu Miclea , Enyedi Szilárd , Gavril Toderean , Alfredo Benso , Paolo Prinetto Towards Microagent based DBIST/DBISR. [Citation Graph (0, 0)][DBLP ] Conf ] David Resnick Embedded Test for a new Memory-Card Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Su , Krishnendu Chakrabarty Concurrent Testing of Droplet-Based Microfluidic Systems for Multiplexed Biomedical Assays. [Citation Graph (0, 0)][DBLP ] Conf ] Tiago R. Balen , Antonio Andrade Jr. , Florence Azaïs , Michel Renovell , Marcelo Lubaszewski Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Muhtaroglu , Benoit Provost , Tawfik Rahal-Arabi , Greg Taylor I/O Self-Leakage Test. [Citation Graph (0, 0)][DBLP ] Conf ] Sreejit Chakravarty , Eric W. Savage , Eric N. Tran Defect Coverage Analysis of Partitioned Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Laung-Terng Wang , Khader S. Abdel-Hafez , Shianling Wu , Xiaoqing Wen , Hiroshi Furukawa , Fei-Sheng Hsu , Shyh-Horng Lin , Sen-Wei Tsai VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Armin Würtenberger , Christofer S. Tautermann , Sybille Hellebrand Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. [Citation Graph (0, 0)][DBLP ] Conf ] Kedarnath J. Balakrishnan , Nur A. Touba Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion. [Citation Graph (0, 0)][DBLP ] Conf ] Baris Arslan , Alex Orailoglu Test Cost Reduction Through A Reconfigurable Scan Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher S. Taillefer , Gordon W. Roberts Reducing Measurement Uncertainty in a DSP-Based Mixed-Signal Test Environment without Increasing Test Time. [Citation Graph (0, 0)][DBLP ] Conf ] H. Mattes , Claus Dworski , S. Sattler Controlled Sine Wave Fitting for ADC Test. [Citation Graph (0, 0)][DBLP ] Conf ] Hideo Okawara Precise Pulse Width Measurement in Write Pre-compensation Test. [Citation Graph (0, 0)][DBLP ] Conf ] José Pineda de Gyvez , Guido Gronthoud , Cristiano Cenci , Martin Posch , Thomas Burger , Manfred Koller Power Supply Ramping for Quasi-static Testing of PLLs. [Citation Graph (0, 0)][DBLP ] Conf ] Masaji Kume , Katsutoshi Uehara , Minoru Itakura , Hideo Sawamoto , Toru Kobayashi , Masatoshi Hasegawa , Hideki Hayashi Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI. [Citation Graph (0, 0)][DBLP ] Conf ] Robert C. Aitken A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Andrei Pavlov , Manoj Sachdev , José Pineda de Gyvez AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. [Citation Graph (0, 0)][DBLP ] Conf ] Osamu Wada , Toshimasa Namekawa , Hiroshi Ito , Atsushi Nakayama , Shuso Fujii Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Shahdad Irajpour , Sandeep K. Gupta , Melvin A. Breuer Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models. [Citation Graph (0, 0)][DBLP ] Conf ] Manan Syal , Michael S. Hsiao , Sreejit Chakravarty Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. [Citation Graph (0, 0)][DBLP ] Conf ] Quming Zhou , Kartik Mohanram Analysis of delay caused by bridging faults in RLC interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Michael S. Hsiao ALAPTF: A new Transition Faultmodel and the ATPG Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Charles Njinda A Hierarchical DFT Architecture for Chip, Board and System Test/Debug. [Citation Graph (0, 0)][DBLP ] Conf ] Sunil Kalidindi , Nghia Huynh , Bill Eklow , Josh Goldstein "Real Life" System Testing of Networking Equipment. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas J. Anderson Practical Instrumentation Integration Considerations. [Citation Graph (0, 0)][DBLP ] Conf ] Baolin Deng , Wolfram Glauert Formal Description of Test Specification and ATE Architecture for Mixed-Signal Test. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Zambaldi , Wolfgang Ecker How to Bridge the Gap Between Simulationand Test. [Citation Graph (0, 0)][DBLP ] Conf ] R. Raghuraman Simulation Requirements for Vectors in ATE Formats. [Citation Graph (0, 0)][DBLP ] Conf ] Bhaskar Chatterjee , Manoj Sachdev , Ali Keshavarzi A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs. [Citation Graph (0, 0)][DBLP ] Conf ] Ramyanshu Datta , Ravi Gupta , Antony Sebastine , Jacob A. Abraham , Manuel A. d'Abreu Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth A. Brand , Erik H. Volkerink , Edward J. McCluskey , Subhasish Mitra Speed Clustering of Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Dongwoo Hong , Chee-Kian Ong , Kwang-Ting (Tim) Cheng BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics. [Citation Graph (0, 0)][DBLP ] Conf ] Peter M. Levine , Gordon W. Roberts A High-Resolution Flash Time-to-Digital Converter and Calibration Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Li , Andy Martwick , Gerry Talbot , Jan B. Wilstrup Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications. [Citation Graph (0, 0)][DBLP ] Conf ] William R. Mann , Frederick L. Taber , Philip W. Seitzer , Jerry J. Broz The Leading Edge of Production Wafer Probe Test Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Qiang Xu , Nicola Nicolici Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Anuja Sehgal , Sandeep Kumar Goel , Erik Jan Marinissen , Krishnendu Chakrabarty IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Kuo-Liang Cheng , Jing-Reng Huang , Chih-Wea Wang , Chih-Yen Lo , Li-Ming Denq , Chih-Tsun Huang , Shin-Wei Hung , Jye-Yuan Lee An SOC Test Integration Platform and Its Industrial Realization. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , T. M. Mak , Martin Omaña Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Man Wah Chiang , Zeljko Zilic , Jean-Samuel Chenard , Katarzyna Radecka Architectures of Increased Availability Wireless Sensor Network Nodes. [Citation Graph (0, 0)][DBLP ] Conf ] Kaijie Wu , Ramesh Karri , Grigori Kuznetsov , Michael Gössel Low Cost Concurrent Error Detection for the Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP ] Conf ] Burnell G. West , Michael F. Jones Digital Synchronization for Reconfigurable ATE. [Citation Graph (0, 0)][DBLP ] Conf ] Daisuke Watanabe , Masakatsu Suda , Toshiyuki Okayasu 34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Gavardoni , Michael Jones , Russell Poffenberger , Miguel Conde System Monitor for Diagnostic, Calibration and System Configuration. [Citation Graph (0, 0)][DBLP ] Conf ] Bipul Chandra Paul , Cassondra Neau , Kaushik Roy Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastià A. Bota , M. Rosales , José Luis Rosselló , Jaume Segura , Ali Keshavarzi Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. [Citation Graph (0, 0)][DBLP ] Conf ] Brady Benware , Cam Lu , John Van Slyke , Prabhu Krishnamurthy , Robert Madge , Martin Keim , Mark Kassab , Janusz Rajski Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. [Citation Graph (0, 0)][DBLP ] Conf ] Andy Kuo , Touraj Farahmand , Nelson Ou , André Ivanov , Sassan Tabatabaei Jitter Models and Measurement Methods for High-Speed Serial Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Gert Hansel , Korbinian Stieglbauer Implementation of an Economic Jitter Compliance Test for a Multi-Gigabit Device on ATE. [Citation Graph (0, 0)][DBLP ] Conf ] Sassan Tabatabaei , Michael Lee , Freddy Ben-Zeev Jitter Generation and Measurement for Test of Multigbps Serial IO. [Citation Graph (0, 0)][DBLP ] Conf ] Shalini Ghosh , Nur A. Touba , Sugato Basu Reducing Power Consumption in Memory ECC Checkers. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Matteo Sonza Reorda , S. Tosato , F. Esposito Evaluating the Effects of Transient Faults on Vehicle Dynamic Performance in Automotive Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Haibo Wang , Suchitra Kulkarni , Spyros Tragoudas On-line Testing Field Programmable Analog Array Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Larsson Integrating Core Selection in the SOC Test Solution Design-Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Ozgur Sinanoglu , Alex Orailoglu Autonomous Yet Deterministic Test of SOC Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Chunsheng Liu , Hamid Sharif , Érika F. Cota , Dhiraj K. Pradhan Test Scheduling for Network-on-Chip with BIST and Precedence Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Hanjun Jiang , Beatriz Olleta , Degang Chen , Randall L. Geiger Testing High Resolution ADCs with Low Resolution/Accuracy Deterministic Dynamic Element Matched DACs. [Citation Graph (0, 0)][DBLP ] Conf ] Hak-soo Yu , Hongjoong Shin , Ji Hwan (Paul) Chun , Jacob A. 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