Conferences in DBLP
José Meseguer Executable Computational Logics: Combining Formal Methods and Programming Language Based System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Romberg , Oscar Slotosch , Gabor Hahn MoDe: A Method for System-Level Architecture Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Luís Gomes , Anikó Costa From Use Cases to System Implementation: Statechart Based Co-design. [Citation Graph (0, 0)][DBLP ] Conf ] Julio A. de Oliveira Filho , Manoel Eusebio de Lima , Paulo Romero Martins Maciel Petri Net Based Interface Analysis for Fast IP-Core Integration. [Citation Graph (0, 0)][DBLP ] Conf ] Islam A. M. El-Maddah , T. S. E. Maibaum Goal-Oriented Requirements Analysis for Process Control Systems Design. [Citation Graph (0, 0)][DBLP ] Conf ] Sander Stuijk , Twan Basten Analyzing Concurrency in Computational Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Margot Bittner , Florian Kammüller Translating Fusion/UML to Object-Z. [Citation Graph (0, 0)][DBLP ] Conf ] Görschwin Fey , Rolf Drechsler Finding Good Counter-Examples to Aid Design Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Edmund M. Clarke , Orna Grumberg , Muralidhar Talupur , Dong Wang High Level Verification of Control Intensive Systems Using Predicate Abstraction. [Citation Graph (0, 0)][DBLP ] Conf ] Sudarshan K. Srinivasan , Miroslav N. Velev Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions. [Citation Graph (0, 0)][DBLP ] Conf ] Magali Contensin , Laurence Pierre Combining ACL2 and a v-calculus Model-Checker to Verify System-Level Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Saito , Kenshu Seto , Yoshihisa Kojima , Satoshi Komatsu , Masahiro Fujita Engineering Changes in Field Modifiable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Grant Martin , Sandeep K. Shukla Hierarchical and Incremental Verification for System Level Design: Challenges and Accomplishments. [Citation Graph (0, 0)][DBLP ] Conf ] Françoise Bellegarde , Celina Charlet , Olga Kouchnarenko How to Compute the Refinement Relation for Parameterized Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Thierry J.-F. Omnés , Gerard Postuma , Jos Verhaegh , Marleen Boonen , Nick Gatherer Using SSDE for USB2.0 conformance co-verification. [Citation Graph (0, 0)][DBLP ] Conf ] Thierry Grandpierre , Yves Sorel From Algorithm and Architecture Specifications to Automatic Generation of Distributed Real-Time Executives: a Seamless Flow of Graphs Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. McMillan Methods for exploiting SAT solvers in unbounded model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Fummi , Graziano Pravadelli , Andrea Fedeli , Umberto Rossi , Franco Toto On the Use of a High-Level Fault Model to Check Properties Incompleteness. [Citation Graph (0, 0)][DBLP ] Conf ] Tobias Schüle , Klaus Schneider Exact Runtime Analysis Using Automata-Based Symbolic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jinfeng Huang , Jeroen Voeten , Marc Geilen Real-time Property Preservation in Approximations of Timed Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sérgio M. M. Fernandes , Paulo Romero Martins Maciel Reliability Evaluation for Dependable Embedded System Specifications: An Approach Based on DSPN. [Citation Graph (0, 0)][DBLP ] Conf ] Manfred Broy Modular Hierarchies of Models for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rohit Jindal , Kshitiz Jain Verification of Transaction-Level SystemC models using RTL Testbenches. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Wodey , Geoffrey Camarroque , Fabrice Baray , Richard Hersemeule , Jean-Philippe Cousin LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Ziller , Klaus Schneider A Generalised Approach to Supervisor Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Dumitru Potop-Butucaru , Robert de Simone Optimizations for Faster Execution of Esterel Programs. [Citation Graph (0, 0)][DBLP ] Conf ] William B. Gardner Bridging CSP and C++ with Selective Formalism and Executable Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Arvind Bluespec: A language for hardware design, simulation, synthesis and verification Invited Talk. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Sprenger , Krzysztof Worytkiewicz A Verification Methodology for Infinite-State Message Passing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] David Cachera , Katell Morin-Allory Verification of Control Properties in the Polyhedral Model. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh K. Gupta , Sandeep K. Shukla Should the space of implementation possibilities be determined by the abilities of high-level synthesis and validation? [Citation Graph (0, 0)][DBLP ] Conf ] Giovanni De Micheli Robust System Design with Uncertain Information. [Citation Graph (0, 0)][DBLP ] Conf ] 