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Conferences in DBLP
- David Baker
A whole new ballgame - supercomputing on two AA batteries (keynote session). [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:3- [Conf]
- Darrell Boggs
Breathing life into a paper tiger (keynote session). [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:5- [Conf]
- Phil Keukes
Defect tolerant molecular electronics: algorithms, architectures, and atoms. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:7- [Conf]
- Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens
Eager writeback - a technique for improving bandwidth utilization. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:11-21 [Conf]
- Kevin M. Lepak, Mikko H. Lipasti
Silent stores for free. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:22-31 [Conf]
- Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:32-41 [Conf]
- Timothy Sherwood, Suleyman Sair, Brad Calder
Predictor-directed stream buffers. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:42-53 [Conf]
- Jared Stark, Mary D. Brown, Yale N. Patt
On pipelining dynamic instruction scheduling logic. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:57-66 [Conf]
- Daniel A. Jiménez, Stephen W. Keckler, Calvin Lin
The impact of delay on the design of branch predictors. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:67-76 [Conf]
- Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson
Improving BTB performance in the presence of DLLs. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:77-86 [Conf]
- Saugata Chatterjee, Chris Weaver, Todd M. Austin
Efficient checker processor design. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:87-97 [Conf]
- Alexandre E. Eichenberger, Waleed Meleis, Suman Maradani
An integrated approach to accelerate data and predicate computations in hyperblocks. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:101-111 [Conf]
- John W. Sias, Wen-mei W. Hwu, David I. August
Accurate and efficient predicate analysis with binary decision diagrams. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:112-123 [Conf]
- F. Jesús Sánchez, Antonio González
Modulo scheduling for a fully-distributed clustered VLIW architecture. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:124-133 [Conf]
- Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
Two-level hierarchical register file organization for VLIW processors. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:137-146 [Conf]
- Yuan C. Chou, Pazhani Pillai, Herman Schmit, John Paul Shen
PipeRench implementation of the instruction path coprocessor. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:147-158 [Conf]
- Ujval J. Kapasi, William J. Dally, Scott Rixner, Peter R. Mattson, John D. Owens, Brucek Khailany
Efficient conditional operations for data-parallel architectures. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:159-170 [Conf]
- Frederik Vermeulen, Lode Nachtergaele, Francky Catthoor, Diederik Verkest, Hugo De Man
Flexible hardware acceleration for multimedia oriented microprocessors. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:171-177 [Conf]
- Ramon Canal, Antonio González, James E. Smith
Very low power pipelines using significance compression. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:181-190 [Conf]
- J. Adam Butts, Gurindar S. Sohi
A static power model for architects. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:191-201 [Conf]
- Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
A framework for dynamic energy efficiency and temperature management. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:202-213 [Conf]
- Luis Villa, Michael Zhang, Krste Asanovic
Dynamic zero compression for cache energy reduction. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:214-220 [Conf]
- Amir Roth, Gurindar S. Sohi
Register integration: a simple and efficient implementation of squash reuse. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:223-234 [Conf]
- Matt Postiff, David Greene, Trevor N. Mudge
The store-load address table and speculative register promotion. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:235-244 [Conf]
- Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:245-257 [Conf]
- Jun Yang, Youtao Zhang, Rajiv Gupta
Frequent value compression in data caches. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:258-265 [Conf]
- Zachary Purser, Karthik Sundaramoorthy, Eric Rotenberg
A study of slipstream processors. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:269-280 [Conf]
- Timothy H. Heil, James E. Smith
Relational profiling: enabling thread-level parallelism in virtual machines. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:281-290 [Conf]
- Markus Mock, Craig Chambers, Susan J. Eggers
Calpa: a tool for automating selective dynamic compilation. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:291-302 [Conf]
- Sanjay J. Patel, Tony Tung, Satarupa Bose, Matthew M. Crum
Increasing the size of atomic instruction blocks using control flow assertions. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:303-313 [Conf]
- Joan-Manuel Parcerisa, Antonio González
Reducing wire delay penalty through value prediction. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:317-326 [Conf]
- Eric Larson, Todd M. Austin
Compiler controlled value prediction using branch predictor based confidence. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:327-336 [Conf]
- Amirali Baniasadi, Andreas Moshovos
Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:337-347 [Conf]
- Tong Liu, Shih-Lien Lu
Performance improvement with circuit-level speculation. [Citation Graph (0, 0)][DBLP]
MICRO, 2000, pp:348-355 [Conf]
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