Conferences in DBLP

PARBASE (parbase)
1990 (conf/parbase/90-2)

1. Doron Tal, Naphtali Rishe, Shamkant B. Navathe, Scott Graham
   On Parallel Architectures. [Citation Graph (0, 0)][DBLP]
   PARBASE / Architectures, 1990, pp:1-17 [Conf]
   
2. C. A. R. Hoare
   A Theory of Conjunction and Concurrency. [Citation Graph (0, 0)][DBLP]
   PARBASE / Architectures, 1990, pp:18-30 [Conf]
   
3. Mohan Ahuja, Kannan Varadhan, Amitabh Sinha
   Flush Message Passing in Communicating Sequential Processes. [Citation Graph (0, 0)][DBLP]
   PARBASE / Architectures, 1990, pp:31-47 [Conf]
   
4. Hessa Al-Jaber, Shmuel Rotenstreich
   Fault Tolerance of Message Delivery with Cascading Copies. [Citation Graph (0, 0)][DBLP]
   PARBASE / Architectures, 1990, pp:48-67 [Conf]
   
5. Suresh Chalasani, Anujan Varma
   Analysis and Simalation of Multistage Interconnection Networks under Non-Uniform Traffic. [Citation Graph (0, 0)][DBLP]
   PARBASE / Architectures, 1990, pp:68-87 [Conf]
   
6. Hyeong-Ah Choi, Bhagirath Narahari, Shmuel Rotenstreich, Abdou Youssef
   Scheduling on Parallel Processing Systems Using Parallel Primitives. [Citation Graph (0, 0)][DBLP]
   PARBASE / Architectures, 1990, pp:88-107 [Conf]
   
7. Arthur F. Dickinson, Ratan K. Guha
   Space Efficient List Merging on a Multiprocessor Ring. [Citation Graph (0, 0)][DBLP]
   PARBASE / Architectures, 1990, pp:108-123 [Conf]
   
8. Jai Eun Jang
   An Optimal Fault-Tolerant Broadcasting Algorithm for a Cube-Connected Cycles Multiprocessor. [Citation Graph (0, 0)][DBLP]
   PARBASE / Architectures, 1990, pp:124-140 [Conf]
   
9. V. Prasad Krothapalli, P. Sadayappan
   Dynamic Scheduling of DOACROSS Loops for Multiprocessors. [Citation Graph (0, 0)][DBLP]
   PARBASE / Architectures, 1990, pp:141-160 [Conf]
   
10. Constantine N. K. Osiakwan, Selim G. Akl
    A Perfect Speedup Parallel Algorithm for the Assignment Problem on Complete Weighted Bipartite Graphs. [Citation Graph (0, 0)][DBLP]
    PARBASE / Architectures, 1990, pp:161-180 [Conf]
    
11. Behrooz Parhami
    Scalable Architectures for VLSI-Based Associative Memories. [Citation Graph (0, 0)][DBLP]
    PARBASE / Architectures, 1990, pp:181-200 [Conf]
    
12. Manohar Rao, Zary Segall
    Implementation and Evaluation of a Parallel PMS Simulator. [Citation Graph (0, 0)][DBLP]
    PARBASE / Architectures, 1990, pp:201-215 [Conf]
    
13. T. D. Roziner
    Systolic Macropipelines for Multidimensional Fourier Transforms. [Citation Graph (0, 0)][DBLP]
    PARBASE / Architectures, 1990, pp:216-230 [Conf]
    
14. Peter J. Varman, Balakrishna R. Iyer, Donald J. Haderle
    Parallel Merging on Shared and Distributed Memory Computers. [Citation Graph (0, 0)][DBLP]
    PARBASE / Architectures, 1990, pp:231-249 [Conf]
    
15. Jie Wu, Eduardo B. Fernández
    The Extended G-Network, a Fault-Tolerant Interconnection Network for the Multiprocessors. [Citation Graph (0, 0)][DBLP]
    PARBASE / Architectures, 1990, pp:250-259 [Conf]
    
16. Qing Yang
    Performance Analysis of a Cache-Coherent Multiprocessor Based on Hierarchical Multiple Buses. [Citation Graph (0, 0)][DBLP]
    PARBASE / Architectures, 1990, pp:260-275 [Conf]
    
17. Qing Yang, Ravi Raja
    Design and Analysis of Multiple-Bus Arbiters with Different Priority Schemes. [Citation Graph (0, 0)][DBLP]
    PARBASE / Architectures, 1990, pp:276-295 [Conf]