Conferences in DBLP

IEEE Symposium on Computer Arithmetic (arith)
2001 (conf/arith/2001)

1. Ruby B. Lee
   Computer Arithmetic-A Processor Architect's Perspective. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2001, pp:3-0 [Conf]
   
2. Martin S. Schmookler, Kevin J. Nowka
   Leading Zero Anticipation and Detection-A Comparison of Methods. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2001, pp:7-12 [Conf]
   
3. Tomás Lang, Jean-Michel Muller
   Bounds on Runs of Zeros and Ones for Algebraic Functions. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2001, pp:13-0 [Conf]
   
4. Peter-Michael Seidel, Lee D. McFearin, David W. Matula
   Binary Multiplication Radix-32 and Radix-256. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2001, pp:23-32 [Conf]
   
5. K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte
   Analysis of Column Compression Multipliers. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2001, pp:33-39 [Conf]
   
6. José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller
   Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2001, pp:40-0 [Conf]
   
7. Jean-Claude Bajard, Laurent-Stéphane Didier, Peter Kornerup
   Modular Multiplication and Base Extensions in Residue Number Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2001, pp:59-65 [Conf]
   
8. M. Anwarul Hasan
   Efficient Computation of Multiplicative Inverses for Cryptographic Applications. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2001, pp:66-72 [Conf]
   
9. Braden Phillips
   Optimised Squaring of Long Integers Using Precomputed Partial Products. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2001, pp:73-0 [Conf]
   
10. Tomás Lang, Elisardo Antelo
    Correctly Rounded Reciprocal Square-Root by Digit Recurrence and Radix-4 Implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:83-93 [Conf]
    
11. Naofumi Takagi
    A Hardware Algorithm for Computing Reciprocal Square Root. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:94-100 [Conf]
    
12. David W. Matula
    Improved Table Lookup Algorithms for Postscaled Division. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:101-0 [Conf]
    
13. Vincent Lefèvre, Jean-Michel Muller
    Worst Cases for Correct Rounding of the Elementary Functions in Double Precision. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:111-118 [Conf]
    
14. Lee D. McFearin, David W. Matula
    Generation and Analysis of Hard to Round Cases for Binary Floating Point Division. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:119-127 [Conf]
    
15. Florent de Dinechin, Arnaud Tisserand
    Some Improvements on Multipartite Table Methods . [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:128-135 [Conf]
    
16. Jun Cao, Belle W. Y. Wei, Jie Cheng
    High-Performance Architectures for Elementary Function Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:136-0 [Conf]
    
17. Michael F. Cowlishaw, Eric M. Schwarz, Ronald M. Smith, Charles F. Webb
    A Decimal Floating-Point Specification. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:147-154 [Conf]
    
18. Yozo Hida, Xiaoye S. Li, David H. Bailey
    Algorithms for Quad-Double Precision Floating Point Arithmetic. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:155-162 [Conf]
    
19. David Lester
    Effective Continued Fractions. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:163-0 [Conf]
    
20. Ajay Naini, Atul Dhablania, Warren James, Debjit Das Sarma
    1-GHz HAL SPARC64 Dual Floating Point Unit with RAS Features. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:173-183 [Conf]
    
21. Peter-Michael Seidel, Guy Even
    On the Design of Fast IEEE Floating-Point Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:184-194 [Conf]
    
22. Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Moon Key Lee, Sang-Woo Kim
    In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:195-0 [Conf]
    
23. Javier D. Bruguera, Tomás Lang
    Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:203-210 [Conf]
    
24. Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
    High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:211-217 [Conf]
    
25. Andrew Beaumont-Smith, Cheng-Chew Lim
    Parallel Prefix Adder Design. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:218-0 [Conf]
    
26. Vassilis Paliouras, Thanos Stouraitis
    Low-Power Properties of the Logarithmic Number System. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:229-236 [Conf]
    
27. Mark G. Arnold, Colin D. Walter
    Unrestricted Faithful Rounding is Good Enough for Some LNS Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:237-246 [Conf]
    
28. Vassil S. Dimitrov, Jonathan Eskritt, Laurent Imbert, Graham A. Jullien, William C. Miller
    The Use of the Multi-Dimensional Logarithmic Number System in DSP Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:247-0 [Conf]
    
29. Sridhar Rajagopal, Joseph R. Cavallaro
    On-line Arithmetic for Detection in Digital Communication Receivers. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:257-265 [Conf]
    
30. Alexandre F. Tenca, Syed Ubaid Hussaini
    A Design of Radix-2 On-line Division Using LSA Organization. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:266-0 [Conf]
    
31. Simon Knowles
    A Family of Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:277-0 [Conf]