Conferences in DBLP
Doran Wilde , Sanjay V. Rajopadhye The naive execution of affine recurrence equations. [Citation Graph (0, 0)][DBLP ] Conf ] Alain Darte , Frédéric Vivien Revisiting the Decomposition of Karp, Miller and Winograd. [Citation Graph (0, 0)][DBLP ] Conf ] Chris J. Scheiman , Peter R. Cappello A Processor-Time-Minimal Schedule for 3D Rectilinear Mesh Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Hyuk-Jae Lee , José A. B. Fortes Data Alignments for Modular Time-Space Mappings of BLAS-like Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Venkatavasu Bokka , Himabindu Gurla , Stephan Olariu , James L. Schwing , Larry Wilson Time-optimal ranking algorithms on sorted matrices. [Citation Graph (0, 0)][DBLP ] Conf ] Yuang-Ming Hsu , Earl E. Swartzlander Jr. , Vincenzo Piuri Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Myung Hoon Sunwoo , Soohwan Ong , Byungdug Ahn , Kyungwoo Lee Design and Implementation of a Parallel Image Processor Chip for a SIMD Array Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Anders Kugler , Roger D. Hersch A Scalable Halftoning Coprocessor Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Ienne Horizontal Microcode Compaction for Programmable Systolic Accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Breveglieri , Luigi Dadda , Vincenzo Piuri Column Compression Pipelined Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Schulte , Earl E. Swartzlander Jr. A Processor for Staggered Interval Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Rong Lin , Stephan Olariu A simple array processor for binary prefix sums. [Citation Graph (0, 0)][DBLP ] Conf ] Raminder Singh Bajwa , Robert Michael Owens , Mary Jane Irwin The MGAP's programming environment and the *C++ language. [Citation Graph (0, 0)][DBLP ] Conf ] B. Saha , J. Sukarno Mertoguno , Nikolaos G. Bourbakis The VLSI design and implementation of the array processors of a multilayer vision system architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein , Jürgen Becker , Rainer Kress , Helmut Reinig , Karin Schmidt A Parallelizing Compilation Method for the Map-oriented Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Amar Mukherjee , Tinku Acharya VLSI Algorithms for Compressed Pattern Search Using Tree Based Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Hughey Parallel Sequence Comparison and Alignment. [Citation Graph (0, 0)][DBLP ] Conf ] D. W. Brown , F. M. F. Gaston The Systolic Design of a Block Regularised Parameter Estimator using Hierarchical Signal Flow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Pascale Guerdoux-Jamet , Dominique Lavenier Systolic Filter for Fast DNA Similarity Search. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Alexander , John L. Ellis , Gershon Kedem A Solid Translation Engine using Ray Representation. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Lang , Andrew Spray Input buffering requirements of a Systolic Array for the Inverse Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Jongwoo Bae , Viktor K. Prasanna Synthesis of VLSI Architectures for Two-Dimensional Discrete Wavelet Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Pierpaolo Baglietto , Massimo Maresca , A. Migliaro , Mauro Migliardi Parallel Implementation of the Full Search Block Matching Algorithm for Motion Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Ronan Barzic , Christian Bouville , François Charot , Gwendal Le Fol , Pascal Lemonnier , Charles Wagner MOVIE: A Building Block for the Design of Real Time Simulator of Moving Pictures Compression Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Heung-Nam Kim , Mary Jane Irwin , Robert Michael Owens Motion Estimation Algorithms on Fine Grain Array Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Yin Chan , Sun-Yuan Kung Bit Level Block Matching Systolic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Zhan Chen , Israel Koren Techniques for Yield Enhancement of VLSI Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph A. Fernando , Jack S. N. Jean Interfacing FPGA/VLSI Processor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Richard K. Squier , Kenneth Steiglitz , Mariusz H. Jakubowski Implementation of Parallel Arithmetic in a Cellular Automaton. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto R. Osorio , Elisardo Antelo , Javier D. Bruguera , Julio Villalba , Emilio L. Zapata Digit On-line Large Radix CORDIC Rotator. [Citation Graph (0, 0)][DBLP ] Conf ] Julio Villalba , J. A. Hidalgo , Emilio L. Zapata , Elisardo Antelo , Javier D. Bruguera CORDIC Architectures with Parallel Compensation of the Scale Factor. [Citation Graph (0, 0)][DBLP ] Conf ] W. Luo , Graham A. Jullien , Neil M. Wigley , William C. Miller , Zhongde Wang An array processor for inner product computations using a Fermat number ALU. [Citation Graph (0, 0)][DBLP ] Conf ] Tudor Jebelean Design of a systolic coprocessor for rational addition. [Citation Graph (0, 0)][DBLP ] Conf ] Valentina P. Markova Multilayer Cellular Algorithm for Complex Number Multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Shuvra S. Bhattacharyya , Sundararajan Sriram , Edward A. Lee Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick M. Lenders , Sanjay V. Rajopadhye Synthesis of Multirate VLSI Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Gérard Ramstein , Olivier Déforges , P. Bakowski A Design Tool for the Specification and the Simulation of Array Processors Architectures - Application to Image Processing: The Extraction of Regions of Interests. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre-Yves Calland , Tanguy Risset Precise Tiling for Uniform Loop Nests. [Citation Graph (0, 0)][DBLP ] Conf ] 