Conferences in DBLP
External Referees. [Citation Graph (0, 0)][DBLP ] Conf ] Program Committee. [Citation Graph (0, 0)][DBLP ] Conf ] Message from the Conference Chairs. [Citation Graph (0, 0)][DBLP ] Conf ] Carl Ebeling Configurable Computing Platforms - Promises, Promises. [Citation Graph (0, 0)][DBLP ] Conf ] Brent E. Nelson The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Bo-Cheng Charles Lai , Patrick Schaumont , Wei Qin , Ingrid Verbauwhede Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Júlio C. B. de Mattos , Stephan Wong , Luigi Carro The Molen FemtoJava Engine. [Citation Graph (0, 0)][DBLP ] Conf ] Antoine Scherrer , Antoine Fraboulet , Tanguy Risset A Generic Multi-Phase On-Chip Traffic Generation Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastian Siegel , Renate Merker Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy. [Citation Graph (0, 0)][DBLP ] Conf ] Masoud Daneshtalab , Ashkan Sobhani , Ali Afzali-Kusha , Omid Fatemi , Zainalabedin Navabi NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Grant Martin Recent Developments in Configurable and Extensible Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey M. Arnold Software Configurable Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Paul L. Master Reconfigurable Hardware and Software Architectural Constructs for the Enablement of Resilient Computing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Drew Taussig , Andreas Hoffmann , Achim Nohl , Andrea Kroll Application Specific Processing: A Tools Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Yedidya Hilewitz , Ruby B. Lee Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Aydin O. Balkan , Gang Qu , Uzi Vishkin A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Tang , Tejas Bhatt , Vishwas Sundaramurthy Reconfigurable Shuffle Network Design in LDPC Decoders. [Citation Graph (0, 0)][DBLP ] Conf ] Ricardo Santos , Rodolfo Azevedo , Guido Araujo 2D-VLIW: An Architecture Based on the Geometry of Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Chuan He , Guan Qin , Mi Lu , Wei Zhao An Efficient Implementation of High-Accuracy Finite Difference Computing Engine on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Lun Li , Alex Fit-Florea , Mitchell A. Thornton , David W. Matula Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Tung N. Pham , Earl E. Swartzlander Jr. Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Aasavari Bhave , Eurípides Montagne , Edgar Granados Describing Quantum Circuits with Systolic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Elie H. Sarraf , Messaoud Ahmed-Ouameur , Daniel Massicotte FPGA Implementation of Beamforming Receivers Based on MRC and NC-LMS for DS-CDMA System. [Citation Graph (0, 0)][DBLP ] Conf ] Daesun Oh , Keshab K. Parhi Low Complexity Design of High Speed Parallel Decision Feedback Equalizers. [Citation Graph (0, 0)][DBLP ] Conf ] Thorsten von Sydow , B. Neumann , Holger Blume , Tobias G. Noll Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep B. Singh , Jayanta Biswas , S. K. Nandy A Cost Effective Pipelined Divider for Double Precision Floating Point Number. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan D. Castellanos , James E. Stine A 64-bit Decimal Floating-Point Comparator. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco J. Jaime , Julio Villalba , Javier Hormigo , Emilio L. Zapata Pipelined Range Reduction for Floating Point Numbers. [Citation Graph (0, 0)][DBLP ] Conf ] Earl E. Swartzlander Jr. Systolic FFT Processors: Past, Present and Future. [Citation Graph (0, 0)][DBLP ] Conf ] John V. McCanny , Roger F. Woods , John G. McWhirter From Bit Level Systolic Arrays to HDTV Processor Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Hughey , Andrea Di Blas The UCSC Kestrel Application-Unspecific Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Peter R. Cappello Multicore processors as Array Processors: Research Opportunities. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas B. Preuber , Rainer G. Spallek Analysis of a Fully-Scalable Digital Fractional Clock Divider. [Citation Graph (0, 0)][DBLP ] Conf ] Mei Kang Qiu , Chun Xue , Qingfeng Zhuge , Zili Shao , Meilin Liu , Edwin Hsing-Mean Sha Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability. [Citation Graph (0, 0)][DBLP ] Conf ] Woo Hyung Lee , Pinaki Mazumder Parallel Processing Based Power Reduction in a 256 State Viterbi Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Ed F. Deprettere , Todor Stefanov , Shuvra S. Bhattacharyya , Mainak Sen Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Clauss , Bénédicte Kenmei Polyhedral Modeling and Analysis of Memory Access Profiles. [Citation Graph (0, 0)][DBLP ] Conf ] Graham A. Jullien Array Processing Using Alternate Arithmetic - A 20 Year Legacy. [Citation Graph (0, 0)][DBLP ] Conf ] Florin Balasa , Per Gunnar Kjeldsberg , Martin Palkovic , Arnout Vandecappelle , Francky Catthoor Loop Transformation Methodologies for Array-Oriented Memory Management. [Citation Graph (0, 0)][DBLP ] Conf ] Kung Yao , Flavio Lorenzelli An Overview of Systolic Array Concepts and Applications for Linear Algebra and Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel P. Lopresti Three Computationally Demanding Problems in Search of ASAP Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Yung Ko , Claudiu Zissulescu , Sebastian Puthenpurayil Parameterized Looped Schedules for Compact Representationof Execution Sequences. [Citation Graph (0, 0)][DBLP ] Conf ] DaeGon Kim , Sanjay V. Rajopadhye An Improved Systolic Architecture for LU Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Shaoxiong Hua , Pushkin R. Pari , Gang Qu Dual-Processor Design of Energy Efficient Fault-Tolerant System. [Citation Graph (0, 0)][DBLP ] Conf ] Giorgos Dimitrakopoulos , Christos Mavrokefalidis , Costas Galanopoulos , Dimitris Nikolos An Energy-Delay Efficient Subword Permutation Unit. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Warsaw , Marcin Lukowiak Architecture design of an H.264/AVC decoder for real-time FPGA implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Antoni Portero , Guillermo Talavera , Marius Monton , Borja Martínez , Francky Catthoor , Jordi Carrabina Dynamic Voltage Scaling for Power Efficient MPEG4-SP Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Bart Mesman , Hamed Fatemi , Henk Corporaal , Twan Basten Dynamic-SIMD for lens distortion compensation. [Citation Graph (0, 0)][DBLP ] Conf ] Herwin Chan , Miguel Griot , Andres I. Vila Casado , Richard D. Wesel , Ingrid Verbauwhede High Speed Channel Coding Architectures for the Uncoordinated OR Channel. [Citation Graph (0, 0)][DBLP ] Conf ] Youtao Zhang , Jun Yang , Lan Gao Efficient Group KeyManagement with Tamper-resistant ISA Extensions. [Citation Graph (0, 0)][DBLP ] Conf ] Guido Bertoni , Luca Breveglieri , Farina Roberto , Francesco Regazzoni Speeding Up AES By Extending a 32 bit Processor Instruction Set. [Citation Graph (0, 0)][DBLP ] Conf ] Youcef Bouchebaba , Gabriela Nicolescu , El Mostapha Aboulhamid , Fabien Coelho Buffer and register allocation for memory space optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Pablo Ituero , Marisa López-Vallejo New Schemes in Clustered VLIW Processors Applied to Turbo Decoding. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Xian , Witawas Srisa-an , Hong Jiang Evaluating Hardware Support for Reference Counting Using Software Configurable Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Yiyu Tan , Chihang Yau , Anthony S. Fong Architectural Support on Object-Oriented Programming in a JAVA Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Humberto Calderon , Stamatis Vassiliadis Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit. [Citation Graph (0, 0)][DBLP ] Conf ] Mythri Alle , Jayanta Biswas , S. K. Nandy High Performance VLSI Architecture Design for H.264 CAVLC Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Gerald R. Morris , Viktor K. Prasanna , Richard D. Anderson An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Hritam Dutta , Frank Hannig , Jürgen Teich , Benno Heigl , Heinz Hornegger A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Neil Smyth , Máire McLoone , John V. McCanny An Adaptable And Scalable Asymmetric Cryptographic Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Guerric Meurice de Dormale , Renaud Ambroise , David Bol , Jean-Jacques Quisquater , Jean-Didier Legat Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Ki Lee , Herwin Chan , Ingrid Verbauwhede Throughput Optimized SHA-1 Architecture Using Unfolding Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Marjan Karkooti , Predrag Radosavljevic , Joseph R. Cavallaro Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] 