Conferences in DBLP
Rolf Drechsler Towards Formal Verification on the System Level. [Citation Graph (0, 0)][DBLP ] Conf ] Ki-Seok Bang , Jin-Young Choi , Sung-Ho Jang Formal Specification and Verification of Embedded System with Shared Resources. [Citation Graph (0, 0)][DBLP ] Conf ] David J. Greaves Automated Hardware Synthesis from Formal Specification Using SAT Solvers. [Citation Graph (0, 0)][DBLP ] Conf ] Swapan Bhattacharyya , Joydeep Bhattacharyya , Adrish Ray Chaudhuri ASET: A Formal Model for System Emulation and Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Doron Drusinsky , Man-tak Shing TLCharts: Armor-plating Harel Statecharts with Temporal Logic Conditions. [Citation Graph (0, 0)][DBLP ] Conf ] Moo-Kyoung Chung , Chong-Min Kyung Improvement of Compiled Instruction Set Simulator by Increasing Flexibility a. [Citation Graph (0, 0)][DBLP ] Conf ] Amjad Mohsen , Richard Hofmann Characterizing Power Consumption and Delay of Functional/Library Components for Hardware/Software Co-Design of Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hideaki Yanagisawa , Minoru Uehara , Hideki Mori Automatic Generation of a Simulation Compiler by a HW/SW Co-Design System. [Citation Graph (0, 0)][DBLP ] Conf ] Chankin Park , Seungmo Cho , Jaewook Lee , Hyungjun Park Co-Validation Environment for Memory Card. [Citation Graph (0, 0)][DBLP ] Conf ] Arnaud Grasset , Frédéric Rousseau , Ahmed Amine Jerraya Network Interface Generation for MPSOC: From Communication Service Requirements to RTL Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] M. De Nobili , R. W. Stewart , G. C. Freeland Rapid Prototyping and Performance Analysis for CDMA2000. [Citation Graph (0, 0)][DBLP ] Conf ] Ying Chen , Dennis Abts , David J. Lilja State Pruning for Test Vector Generation for a Multiprocessor Cache Coherence Protocol. [Citation Graph (0, 0)][DBLP ] Conf ] Ferid Gharsalli , Amer Baghdadi , Marius Bonaciu , Giedrius Majauskas , Wander O. Cesário , Ahmed Amine Jerraya An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Adriano Sarmento , Wander O. Cesário , Ahmed Amine Jerraya Automatic Building of Executable Models from Abstract SoC Architectures Made of Heterogeneous Subsystems. [Citation Graph (0, 0)][DBLP ] Conf ] Rawat Siripokarpirom , Friedrich Mayer-Lindenberg Hardware-Assisted Simulation and Evaluation of IP Cores Using FPGA-Based Rapid Prototyping Boards. [Citation Graph (0, 0)][DBLP ] Conf ] M. Diaby , Matthieu Tuna , Jean Lou Desbarbieux , Franck Wajsbürt High Level Synthesis Methodology from C to FPGA Used for a Network Protocol Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Shane Sendall Domain Driven Software Development -- A World of Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Pavle Belanovic , Martin Holzer 0002 , Bastian Knerr , Markus Rupp , Guillaume Sauzon Automatic Generation of Virtual Prototypes. [Citation Graph (0, 0)][DBLP ] Conf ] Kang Zhang , Guang-Lei Song , Jun Kong Rapid Software Prototyping Using Visual Language Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Frédéric Gilliers , Jean-Pierre Velu , Fabrice Kordon Generation of Distributed Programs in Their Target Execution Environment. [Citation Graph (0, 0)][DBLP ] Conf ] George M. Lawler , Paul E. Young Approaching Interoperability from the Bottom up: A Lattice Structure for the Object-Oriented Method for Interoperability (OOMI). [Citation Graph (0, 0)][DBLP ] Conf ] André Meisel , Markus Visarius , Wolfram Hardt , Stefan Ihmor Self-Reconfiguration of Communication Interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Denning , James Irvine , Derek Stark , Malachy Devlin Multi-User FPGA Co-Simulation over TCP/IP. [Citation Graph (0, 0)][DBLP ] Conf ] Camel Tanougast , Yves Berviller , Christian Mannino , Hassan Rabah , Michael Janiaut , Serge Weber SystemC Model of a MPEG-2 DVB-T Bit-Rate Measurement Architecture for FPGA Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth B. Kent , Hejun Ma , Micaela Serra Rapid Prototyping of a Co-Designed Java Virtual Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos Papandreou , Maria Varsamou , Theodore Antonakopoulos Transmission Systems Prototyping Based on Stateflow/Simulink Models. [Citation Graph (0, 0)][DBLP ] Conf ] Apostolos Dollas , Kyprianos Papademetriou , Euripides Sotiriades , Dimitrios Theodoropoulos , Iosif Koidis , George Vernardos A Case Study on Rapid Prototyping of Hardware Systems: The Effect of CAD Tool Capabilities, Design Flows, and Design Styles. [Citation Graph (0, 0)][DBLP ] Conf ] Ralf Ludewig , Thomas Hollstein , Falko Schütz , Manfred Glesner Rapid Prototyping of an Integrated Testing and Debugging Unit. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Martinelli , Armin Wellig , Julien Zory Transaction-Level Prototyping of a UMTS Outer-Modem for System-on-Chip Validation and Architecture Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] James Bret Michael , Man-tak Shing , Michael H. Miklaski , Joel D. Babbitt Modeling and Simulation of System-of-Systems Timing Constraints with UML-RT and OMNeT++. [Citation Graph (0, 0)][DBLP ] Conf ] Fabiano Hessel , Vitor M. da Rosa , Igor M. Reis , Ricardo Planner , César A. M. Marcon , Altamiro Amadeu Susin Abstract RTOS Modeling for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sylvain Alliot , Ed F. Deprettere Architecture Exploration of a Large Scale System. [Citation Graph (0, 0)][DBLP ] Conf ] Maryse Wouters , Peter Van Wesemael , Roeland Vandebriel , Andy Dewilde , Michael Libois Real Time Prototyping of Broadband Wireless LAN Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Moisès Serra , Pere Martí , Jordi Carrabina Implementation of a Channel Equalizer for OFDM Wireless LANs. [Citation Graph (0, 0)][DBLP ] Conf ] Yann Thoma , Eduardo Sanchez , Daniel Roggen , Carl Hetherington , Juan Manuel Moreno Prototyping with a Bio-Inspired Reconfigurable Chip. [Citation Graph (0, 0)][DBLP ] Conf ] 