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Conferences in DBLP

IEEE International Workshop on Rapid System Prototyping (rsp)
2005 (conf/rsp/2005)


  1. Conference Committees. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:- [Conf]

  2. Message from the General Chairs. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:- [Conf]

  3. Message from the Organizing Chair. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:- [Conf]

  4. Message from the Program Chairs. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:- [Conf]
  5. Stefan Ihmor, Tobias Loke, Wolfram Hardt
    Synthesis of Communication Structures and Protocols in Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:3-9 [Conf]
  6. Matthieu Briere, Emmanuel Drouard, Fabien Mieyeville, David Navarro, Ian O'Connor, Frédéric Gaffiot
    Heterogeneous Modelling of an Optical Network-on-Chip with SystemC. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:10-16 [Conf]
  7. César A. M. Marcon, Márcio Eduardo Kreutz, Altamiro Amadeu Susin, Ney Laert Vilar Calazans
    Models for Embedded Application Mapping onto NoCs: Timing Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:17-23 [Conf]
  8. R. Lemaire, Fabien Clermidy, Y. Durand, D. Lattard, Ahmed Amine Jerraya
    Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:24-30 [Conf]
  9. James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu
    Leveraging Model Representations for System Level Design Tools. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:33-39 [Conf]
  10. Chia-Jui Hsu, Shuvra S. Bhattacharyya
    Porting DSP Applications across Design Tools Using the Dataflow Interchange Format. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:40-46 [Conf]
  11. Arnaud Grasset, Frédéric Rousseau, Ahmed Amine Jerraya
    Automatic Generation of Component Wrappers by Composition of Hardware Library Elements Starting from Communication Service Specification. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:47-53 [Conf]
  12. Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley, Jean-Pierre David
    High Level Synthesis for Data-Driven Applications. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:54-60 [Conf]
  13. Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi
    Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:63-69 [Conf]
  14. Markus Visarius, André Meisel, Markus Scheithauer, Wolfram Hardt
    Dynamic Reconfiguration of IP-Based Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:70-76 [Conf]
  15. Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo
    Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:77-83 [Conf]
  16. Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
    A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:84-90 [Conf]
  17. Ghulam Qader, M. Younus Javed
    Simulation of Resolution of CS Problem for Multiple Common Variables in Multiprocessor Environment. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:93-98 [Conf]
  18. John Carter, Ming Xu, W. B. Gardner
    Rapid Prototyping of Embedded Software Using Selective Formalism. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:99-104 [Conf]
  19. Doron Drusinsky, Man-tak Shing, Kadir Alpaslan Demir
    Test-Time, Run-Time, and Simulation-Time Temporal Assertions in RSP. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:105-110 [Conf]
  20. Thomas Vergnaud, Jérôme Hugues, Laurent Pautet, Fabrice Kordon
    Rapid Development Methodology for Customized Middleware. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:111-117 [Conf]
  21. Deepak Argarwal, Christopher R. Anderson, Peter M. Athanas
    An 8-GHz Ultra Wideband Transceiver Prototyping Testbed. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:121-127 [Conf]
  22. Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel
    Enabling a Real-Time Solution for Neuron Detection with Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:128-134 [Conf]
  23. Carsten Bieser, Klaus D. Müller-Glaser
    COMPASS - A Novel Concept of a Reconfigurable Platform for Automotive System Development and Test. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:135-140 [Conf]
  24. Benny Thörnberg, Leif Olsson, Mattias O'Nils
    Optimization of Memory Allocation for Real-Time Video Processing on FPGA. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:141-147 [Conf]
  25. Kugan Vivekanandarajah, Thambipillai Srikanthan
    Custom Instruction Filter Cache Synthesis for Low-Power Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:151-157 [Conf]
  26. Moo-Kyoung Chung, Heejun Shim, Chong-Min Kyung
    Performance Improvement of Multiprocessor Simulation by Optimizing Synchronization a Communication. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:158-164 [Conf]
  27. Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
    Optimization Techniques for ADL-Driven RTL Processor Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:165-171 [Conf]
  28. Pavle Belanovic, Markus Rupp
    Automated Floating-Point to Fixed-Point Conversion with the Fixify Environment. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:172-178 [Conf]
  29. Faouzi Bouchhima, Gabriela Nicolescu, El Mostapha Aboulhamid, Mohamed Abid
    Discrete-Continuous Simulation Model for Accurate Validation in Component-Based Heterogeneous SoC Design. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:181-187 [Conf]
  30. Mikhail Auguston, James Bret Michael, Man-tak Shing
    Test Automation and Safety Assessment in Rapid Systems Prototyping. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:188-194 [Conf]
  31. Levi Lucio, Luis Pedro, Didier Buchs
    A Test Language for CO-OPN Specifications. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:195-201 [Conf]
  32. Chadlia Jerad, Kamel Barkaoui
    On the Use of Rewriting Logic for Verification of Distributed Software Architecture Description Based LfP. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:202-208 [Conf]
  33. Silvio Dragone, Clemens Lombriser
    The Ordering of Events in a Prototyping Platform. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:211-217 [Conf]
  34. Ivan Petkov, Paul Amblard, Marin Hristov
    Systematic Design Flow for Fast Hardware/Software Prototype Generation from Bus Functional Model for MPSoC. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:218-224 [Conf]
  35. Leandro Soares Indrusiak, Romualdo Begale Prudencio, Manfred Glesner
    Modeling and Prototyping of Communication Systems Using Java: A Case Study. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:225-231 [Conf]
  36. Martin Irman, Jan Bajcsy
    A Rapid System Prototyping Platform for Error Control Coding in Optical CDMA Networks. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:232-234 [Conf]
  37. Sanggyu Park, Soo-Ik Chae
    A C/C++-Based Functional Verification Framework Using the SystemC Verification Library. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:237-239 [Conf]
  38. Sylvain Huet, Emmanuel Casseau, Olivier Pasquier
    Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:240-243 [Conf]
  39. Luke Demoracski, Dimiter R. Avresky
    An Approach for Functional Decomposition Applied to State-Based Designs. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:243-245 [Conf]
  40. Adrian Chirila-Rus, Kristof Denolf, Bart Vanhoof, Paul R. Schumacher, Kees A. Vissers
    Communication Primitives Driven Hardware Design and Test Methodology Applied on Complex Video Applications. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:246-249 [Conf]
  41. Thomas S. Hall, Kenneth B. Kent
    Thread-Level Parallel Execution in Co-Designed Virtual Machines. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:249-251 [Conf]
  42. Arnaldo Azevedo, Luciano Volcan Agostini, Flávio Rech Wagner, Sergio Bampi
    Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:255-257 [Conf]
  43. Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große
    SyCE: An Integrated Environment for System Design in SystemC. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:258-260 [Conf]
  44. Nikolaos Kostaras, Haridimos T. Vergos
    KoVer: A Sophisticated Residue Arithmetic Core Generator. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:261-263 [Conf]
  45. Ami Castonguay, Yvon Savaria
    A HyperTransport Chip-to-Chip Interconnect Tunnel Developed Using SystemC. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:264-266 [Conf]
  46. S. W. Song, J. D. Zheng, W. B. Gardner
    Prototyping a Residential Gateway Using Xilinx ISE. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:267-269 [Conf]
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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