Conferences in DBLP
D. A. Gilbert , Jim D. Garside A Result Forwarding Mechanism for Asynchronous Pipelined Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sam S. Appleton , Shannon V. Morton , Michael J. Liebelt Two-Phase Asynchronous Pipeline Control. [Citation Graph (0, 0)][DBLP ] Conf ] O. A. Petlin , Stephen B. Furber Built-In Self-Testing of Micropipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Peggy B. K. Pang , Mark R. Greenstreet Self-Timed Meshes Are Faster Than Synchronous. [Citation Graph (0, 0)][DBLP ] Conf ] Priyadarsan Patra , Stanislav Polonsky , Donald S. Fussell Delay Insensitive Logic for RSFQ Superconductor Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Riccardo Mariani , R. Roncella , Roberto Saletti , Pierangelo Terreni On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Aiguo Xie , Peter A. Beerel Symbolic Techniques for Performance Analysis of Timed Systems Based on Average Time Separation of Events. [Citation Graph (0, 0)][DBLP ] Conf ] Jo C. Ebergen , Robert Berks Response Time Properties of Some Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Wendy Belluomini , Chris J. Myers Efficient Timing Analysis Algorithms for Timed State Space Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Supratik Chakraborty , David L. Dill , Kun-Yung Chang , Kenneth Y. Yun Timing Analysis of Extended Burst-Mode Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Supratik Chakraborty , David L. Dill More Accurate Polynomial-Time Min-Max Timing Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro A. Molina , Peter Y. K. Cheung A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Y. Yun , Ayoob E. Dooply , Julio Arceo , Peter A. Beerel , Vida Vakilotojar The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver. [Citation Graph (0, 0)][DBLP ] Conf ] Juha Plosila , Kaisa Sere Action Systems in Pipelined Processor Design. [Citation Graph (0, 0)][DBLP ] Conf ] Paul G. Lucassen , Indra Polak , Jan Tijmen Udding Normal Form in DI-Algebra with Recursion. [Citation Graph (0, 0)][DBLP ] Conf ] Willem C. Mallon , Jan Tijmen Udding Using Metrics for Proof Rules for Recursively Defined Delay-insensitive Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Kearney , Neil W. Bergmann Bundled Data Asynchronous Multipliers with Data Dependent Computation Times. [Citation Graph (0, 0)][DBLP ] Conf ] Gensoh Matsubara , Nobuhiro Ide A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Steven M. Nowick , Kenneth Y. Yun , Ayoob E. Dooply , Peter A. Beerel Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders. [Citation Graph (0, 0)][DBLP ] Conf ] J. W. J. M. Rutten , Michel R. C. M. Berkelaar Improved State Assignment for Burst Mode Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Kondratyev , Michael Kishinevsky , Jordi Cortadella , Luciano Lavagno , Alexandre Yakovlev Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Alexei L. Semenov , Alexandre Yakovlev , Enric Pastor , Marco A. Peña , Jordi Cortadella , Luciano Lavagno Partial order based approach to synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Joep L. W. Kessels , Paul Marston Designing Asynchronous Standby Circuits for a Low-Power Pager. [Citation Graph (0, 0)][DBLP ] Conf ] Charles E. Molnar , Ian W. Jones , William S. Coates , Jon K. Lexau A FIFO Ring Performance Experiment. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen B. Furber , Jim D. Garside , Steve Temple , Jianwei Liu , P. Day , N. C. Paver AMULET2e: An Asynchronous Embedded Controller. [Citation Graph (0, 0)][DBLP ] Conf ] 