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Ramachandran Vaidyanathan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hettihe P. Dharmasena, Ramachandran Vaidyanathan
    An Optimal Multiple Bus Network for Fan-in Algorithms. [Citation Graph (0, 0)][DBLP]
    ICPP, 1997, pp:12-15 [Conf]
  2. Hettihe P. Dharmasena, Ramachandran Vaidyanathan
    An Optimal Multiple Bus Network for Fan-in Algorithms. [Citation Graph (0, 0)][DBLP]
    ICPP, 1997, pp:100-0 [Conf]
  3. Omkar M. Dighe, Ramachandran Vaidyanathan, Si-Qing Zheng
    Bus-Based Tree Structures for Efficient Parallel Computation. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:158-161 [Conf]
  4. Chittur Subbaraman, Jerry L. Trahan, Ramachandran Vaidyanathan
    List Ranking and Graph Algorithms on the Reconfigurable Multiple Bus Machine. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:244-247 [Conf]
  5. Jerry L. Trahan, Ramachandran Vaidyanathan, Chittur Subbaraman
    Constant Time Graph and Poset Algorithms on the Reconfigurable Multiple Bus Machine. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1994, pp:214-217 [Conf]
  6. Ramachandran Vaidyanathan, Karthik Sethuraman
    On Mapping Multidimensional Weak Tori on Optical Slab Waveguides. [Citation Graph (0, 0)][DBLP]
    ICPP, 2005, pp:219-226 [Conf]
  7. Hettihe P. Dharmasena, Ramachandran Vaidyanathan
    Lower Bounds on the Loading of Degree-2 Multiple Bus Networks for Binary-Tree Algorithms. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1999, pp:21-25 [Conf]
  8. Hatem M. El-Boghdadi, Ramachandran Vaidyanathan, Jerry L. Trahan, Suresh Rai
    On the Communication Capability of the Self-Reconfigurable Gate Array Architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  9. Martin Feldman, Ramachandran Vaidyanathan, Ahmed El-Amawy
    High Speed, High Capacity Bused Interconnects using Optical Slab Waveguides. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:924-937 [Conf]
  10. José Alberto Fernández-Zepeda, Ramachandran Vaidyanathan, Jerry L. Trahan
    Improved Scaling Simulation of the General Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:616-624 [Conf]
  11. Krishnendu Roy, Ramachandran Vaidyanathan, Jerry L. Trahan
    Configuring the Circuit Switched Tree for Multiple Width Communications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  12. Nitin Srivastava, Jerry L. Trahan, Ramachandran Vaidyanathan, Suresh Rai
    Adaptive Image Filtering Using Run-Time Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:180- [Conf]
  13. Ratnapuri K. Thiruchelvan, Jerry L. Trahan, Ramachandran Vaidyanathan
    On the Power of Segmenting and Fusing Buses. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:79-83 [Conf]
  14. Ramachandran Vaidyanathan, Carlos R. P. Hartmann, Pramod K. Varshney
    Towards Optimal Parallel Radix Sorting. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:193-197 [Conf]
  15. Ramachandran Vaidyanathan, Sudharani Nadella
    Fault-Tolerant Multiple Bus Networks for Fan-In Algorithms. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:674-681 [Conf]
  16. Jerry L. Trahan, Anu G. Bourgeois, Ramachandran Vaidyanathan, Yi Pan
    Optimally Scaling Permutation Routing on Reconfigurable Linear Arrays with Optical Buses. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1999, pp:233-0 [Conf]
  17. Jerry L. Trahan, Chun-ming Lu, Ramachandran Vaidyanathan
    Integer and Floating Point Matrix-Vector Multiplication on the Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:702-706 [Conf]
  18. Martin Feldman, Ahmed El-Amawy, Ramachandran Vaidyanathan
    Free Space All-optical Crossconnect. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2002, pp:823-828 [Conf]
  19. Hettihe P. Dharmasena, Ramachandran Vaidyanathan
    Fault Tolerance in Multiple Bus Networks with Unbalanced Resource Utilization. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:247-254 [Conf]
  20. Hatem M. El-Boghdadi, Ramachandran Vaidyanathan, Jerry L. Trahan, Suresh Rai
    Reconfigurable Mesh on the Reconfigurable Tree Array. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2002, pp:1068-1074 [Conf]
  21. Hatem M. El-Boghdadi, Ramachandran Vaidyanathan, Jerry L. Trahan, Suresh Rai
    On Designing Implementable Algorithms for the Linear Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:241-246 [Conf]
  22. Ramachandran Vaidyanathan, Carlos R. P. Hartmann, Pramod K. Varshney
    Parallel Integer Sorting Using Small Operations [Citation Graph (0, 0)][DBLP]
    Acta Inf., 1995, v:32, n:1, pp:79-92 [Journal]
  23. Yi Pan, Jerry L. Trahan, Ramachandran Vaidyanathan
    A Scalable and Efficient Algorithm for Computing the City Block Distance Transform on Reconfigurable Meshes. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1997, v:40, n:7, pp:435-440 [Journal]
  24. Krishnendu Roy, Ramachandran Vaidyanathan, Jerry L. Trahan
    Routing Multiple Width Communications on the Circuit Switched Tree. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 2006, v:17, n:2, pp:271-286 [Journal]
  25. Jerry L. Trahan, Ramachandran Vaidyanathan
    Scaling multiple addition and prefix sums on the reconfigurable mesh. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2002, v:82, n:6, pp:277-282 [Journal]
  26. Ramachandran Vaidyanathan
    Sorting on PRAMs with Reconfigurable Buses. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1992, v:42, n:4, pp:203-208 [Journal]
  27. Ramachandran Vaidyanathan, Carlos R. P. Hartmann, Pramod K. Varshney
    PRAMs with Variable Word-Size. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1992, v:42, n:4, pp:217-222 [Journal]
  28. Ramachandran Vaidyanathan, Carlos R. P. Hartmann, Pramod K. Varshney
    Running ASCEND, DESCEND and PIPELINE Algorithms in Parallel Using Small Processors. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1993, v:46, n:1, pp:31-36 [Journal]
  29. Ramachandran Vaidyanathan, Jerry L. Trahan
    Optimal Simulation of Multidimensional Reconfigurable Meshes by Two-Dimensional Reconfigurable Meshes. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1993, v:47, n:5, pp:267-273 [Journal]
  30. Hettihe P. Dharmasena, Ramachandran Vaidyanathan
    The Mesh With Binary Tree Networks: An Enhanced Mesh With Low Bus-Loading. [Citation Graph (0, 0)][DBLP]
    Journal of Interconnection Networks, 2004, v:5, n:2, pp:131-150 [Journal]
  31. Omkar M. Dighe, Ramachandran Vaidyanathan, Si-Qing Zheng
    The Bus-Connected Ringed Tree: A Versatile Interconnection Network. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1996, v:33, n:2, pp:189-196 [Journal]
  32. José Alberto Fernández-Zepeda, Ramachandran Vaidyanathan, Jerry L. Trahan
    Using Bus Linearization to Scale the Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2002, v:62, n:4, pp:495-516 [Journal]
  33. Jerry L. Trahan, Anu G. Bourgeois, Yi Pan, Ramachandran Vaidyanathan
    Optimally Scaling Permutation Routing on Reconfigurable Linear Arrays with Optical Buses. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2000, v:60, n:9, pp:1125-1136 [Journal]
  34. Jerry L. Trahan, Ramachandran Vaidyanathan, Chittur Subbaraman
    Constant Time Graph Algorithms on the Reconfigurable Mutliple Buss Machine. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1997, v:46, n:1, pp:1-14 [Journal]
  35. Jerry L. Trahan, Ramachandran Vaidyanathan, Ratnapuri K. Thiruchelvan
    On the Power of Segmenting and Fusing Buses. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1996, v:34, n:1, pp:82-94 [Journal]
  36. Ramachandran Vaidyanathan, Anand Padmanabhan
    Bus-Based Networks for Fan-In and Uniform Hypercube Algorithms. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1995, v:21, n:11, pp:1807-1821 [Journal]
  37. Ramachandran Vaidyanathan, Jerry L. Trahan, Chun-ming Lu
    Degree of scalability: scalable reconfigurable mesh algorithms for multiple addition and matrix-vector multiplication. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2003, v:29, n:1, pp:95-109 [Journal]
  38. Jerry L. Trahan, Anu G. Bourgeois, Ramachandran Vaidyanathan
    Tighter and Broader Complexity Results for Reconfigurable Models. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1998, v:8, n:3, pp:271-282 [Journal]
  39. Hettihe P. Dharmasena, Ramachandran Vaidyanathan
    Lower Bounds on the Loading of Multiple Bus Networks for Binary Tree Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:12, pp:1535-1546 [Journal]
  40. Arshad Ali, Ramachandran Vaidyanathan
    Exact Bounds on Running ASCEND/DESCEND and FAN-IN Algorithms on Synchronous Multiple Bus Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1996, v:7, n:8, pp:783-790 [Journal]
  41. José Alberto Fernández-Zepeda, Ramachandran Vaidyanathan, Jerry L. Trahan
    Scaling Simulation of the Fusing-Restricted Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:9, pp:861-871 [Journal]

  42. Configurable decoders with application in fast partial reconfiguration of FPGAs. [Citation Graph (, )][DBLP]


  43. Input-queued switches with logarithmic delay: necessary conditions and a reconfigurable scheduling algorithm. [Citation Graph (, )][DBLP]


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