Conferences in DBLP

Design, Automation, and Test in Europe (date)
2003 (conf/date/2003)

1. Emile H. L. Aarts, Raf Roovers
   IC Design Challenges for Ambient Intelligence. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10002-10007 [Conf]
   
2. Andrea Cuomo
   Semiconductor Challenges. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10008-10009 [Conf]
   
3. Menno Lindwer, Diana Marculescu, Twan Basten, Rainer Zimmermann, Radu Marculescu, Stefan Jung, Eugenio Cantatore
   Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10010-10017 [Conf]
   
4. Alberto Macii, Enrico Macii, Massimo Poncino
   Improving the Efficiency of Memory Partitioning by Address Clustering. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10018-10023 [Conf]
   
5. Alberto Macii, Enrico Macii, Fabrizio Crudo, Roberto Zafalon
   A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10024-10029 [Conf]
   
6. Peter Petrov, Alex Orailoglu
   Power Efficiency through Application-Specific Instruction Memory Transformations. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10030-10035 [Conf]
   
7. Marcos Sanchez-Elez, Milagros Fernández, Manuel L. Anido, Haitao Du, Nader Bagherzadeh, Román Hermida
   Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10036-10043 [Conf]
   
8. Bill Grundmann, Rajesh Galivanche, Sandip Kundu
   Circuit and Platform Design Challenges in Technologies beyond 90nm. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10044-10049 [Conf]
   
9. Li-Da Huang, Hung-Ming Chen, D. F. Wong
   Global Wire Bus Configuration with Minimum Delay Uncertainty. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10050-10055 [Conf]
   
10. Hai Zhou
    Timing Verification with Crosstalk for Transparently Latched Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10056-10061 [Conf]
    
11. Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
    Statistical Timing Analysis Using Bounds. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10062-10067 [Conf]
    
12. Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman
    Reduced Delay Uncertainty in High Performance Clock Distribution Networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10068-10075 [Conf]
    
13. Twan Basten, Luca Benini, Anantha Chandrakasan, Menno Lindwer, Jie Liu, Rex Min, Feng Zhao
    Scaling into Ambient Intelligence. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10076-10083 [Conf]
    
14. Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, R. R. Brooks, Soontae Kim, Wei Zhang 0002
    Masking the Energy Behavior of DES Encryption. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10084-10089 [Conf]
    
15. Dong Wu, Bashir M. Al-Hashimi, Petru Eles
    Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10090-10095 [Conf]
    
16. Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy
    Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10096-10103 [Conf]
    
17. Wenjing Rao, Alex Orailoglu
    Virtual Compression through Test Vector Stitching for Scan Based Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10104-10109 [Conf]
    
18. Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch
    Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10110-10115 [Conf]
    
19. Michael J. Knieser, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, David R. McIntyre
    A Technique for High Ratio LZW Compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10116-10121 [Conf]
    
20. Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski
    Fast Computation of Data Correlation Using BDDs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10122-10129 [Conf]
    
21. Andreas Gerstlauer, Haobo Yu, Daniel Gajski
    RTOS Modeling for System Level Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10130-10135 [Conf]
    
22. Shaojie Wang, Sharad Malik, Reinaldo A. Bergamaschi
    Modeling and Integration of Peripheral Devices in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10136-10141 [Conf]
    
23. F. Herrera, Hector Posadas, Pablo Sánchez, Eugenio Villar
    Systemic Embedded Software Generation from SystemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10142-10149 [Conf]
    
24. Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi
    Noise Macromodel for Radio Frequency Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10150-10155 [Conf]
    
25. Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney
    Approximation Approach for Timing Jitter Characterization in Circuit Simulators. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10156-10161 [Conf]
    
26. Ewout Martens, Georges G. E. Gielen
    A Model of Computation for Continuous-Time ?-? Modulators. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10162-10167 [Conf]
    
27. R. Castro-López, Francisco V. Fernández, F. Medeiro, Ángel Rodríguez-Vázquez
    Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10168-10175 [Conf]
    
28. Anand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater
    Securing Mobile Appliances: New Challenges for the System Designer. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10176-10183 [Conf]
    
29. Paul Pop, Petru Eles, Zebo Peng
    Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10184-10189 [Conf]
    
30. Samarjit Chakraborty, Simon Künzli, Lothar Thiele
    A General Framework for Analysing System Properties in Platform-Based Embedded System Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10190-10195 [Conf]
    
31. George Logothetis, Klaus Schneider
    Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10196-10203 [Conf]
    
32. Bernhard Rinner, Martin Schmid, Reinhold Weiss
    Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10204-10211 [Conf]
    
33. Muhammad Nummer, Manoj Sachdev
    DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10212-10217 [Conf]
    
34. Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani
    Extending JTAG for Testing Signal Integrity in SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10218-10223 [Conf]
    
35. Dhiraj K. Pradhan, Chunsheng Liu, Krishnendu Chakrabarty
    EBIST: A Novel Test Generator with Built-In Fault Detection Capability. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10224-10229 [Conf]
    
36. Chunsheng Liu, Krishnendu Chakrabarty
    A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10230-10237 [Conf]
    
37. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
    Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10238-10243 [Conf]
    
38. Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney
    A New Simulation Technique for Periodic Small-Signal Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10244-10249 [Conf]
    
39. Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
    Generalized Posynomial Performance Modeling. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10250-10255 [Conf]
    
40. Bart De Smedt, Georges G. E. Gielen
    HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10256-10263 [Conf]
    
41. María C. Molina, José M. Mendías, Román Hermida
    High-Level Allocation to Minimize Internal Hardware Wastage. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10264-10269 [Conf]
    
42. Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau
    Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10270-10275 [Conf]
    
43. Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya
    Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10276-10281 [Conf]
    
44. Kyeong Keol Ryu, Vincent John Mooney
    Automated Bus Generation for Multiprocessor SoC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10282-10289 [Conf]
    
45. Herbert Walder, Marco Platzner
    Online Scheduling for Block-Partitioned Reconfigurable Devices . [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10290-10295 [Conf]
    
46. Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins
    Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10296-10301 [Conf]
    
47. Sebastian Lange, Udo Kebschull
    Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10302-10309 [Conf]
    
48. Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara
    A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10310-10315 [Conf]
    
49. Manan Syal, Michael S. Hsiao
    A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10316-10321 [Conf]
    
50. Saravanan Padmanaban, Spyros Tragoudas
    Non-Enumerative Path Delay Fault Diagnosis . [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10322-10327 [Conf]
    
51. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir
    Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10328-10335 [Conf]
    
52. Sungjoo Yoo, Ahmed Amine Jerraya
    Introduction to Hardware Abstraction Layers for SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10336-10337 [Conf]
    
53. Vincent John Mooney
    Hardware/Software Partitioning of Operating Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10338-10339 [Conf]
    
54. M. Sarlotte, B. Candaele, J. Quevremont, D. Merel
    Embedded Software in Digital AM-FM Chipset. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10340-10343 [Conf]
    
55. Terry Tao Ye, Luca Benini, Giovanni De Micheli
    Packetized On-Chip Interconnect Communication Analysis for MPSoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10344-10349 [Conf]
    
56. Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, E. Waterlander
    Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10350-10355 [Conf]
    
57. Frank Gilbert, Michael J. Thul, Norbert Wehn
    Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors . [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10356-10363 [Conf]
    
58. Ingo Sander, Axel Jantsch, Zhonghai Lu
    Development and Application of Design Transformations in ForSyDe. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10364-10369 [Conf]
    
59. Satnam Singh
    System Level Specification in Lava. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10370-10375 [Conf]
    
60. Ashraf Salem
    Formal Semantics of Synchronous SystemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10376-10381 [Conf]
    
61. Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta
    Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10382-10387 [Conf]
    
62. Alain Vachoux, Christoph Grimm, Karsten Einwich
    SystemC-AMS Requirements, Design Objectives and Rationale. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10388-10395 [Conf]
    
63. Kees A. Vissers
    Parallel Processing Architectures for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10396-10397 [Conf]
    
64. Bhusan Gupta, Michele Borgatti
    Different Approaches to Add Reconfigurability in a SoC Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10398-10398 [Conf]
    
65. Brandon Blodget, Scott McMillan, Patrick Lysaght
    A Lightweight Approach for Embedded Reconfiguration of FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10399-10401 [Conf]
    
66. Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Müller
    Creating Value Through Test. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10402-10409 [Conf]
    
67. Heiko Falk, Peter Marwedel
    Control Flow Driven Splitting of Loop Nests at the Source Code Level . [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10410-10415 [Conf]
    
68. Mahmut T. Kandemir, Guangyu Chen, Wei Zhang 0002, Ibrahim Kolcu
    Data Space Oriented Scheduling in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10416-10421 [Conf]
    
69. Satish Pillai, Margarida F. Jacome
    Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10422-10427 [Conf]
    
70. Antonio G. Lomeña, Marisa Luisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev
    An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10428-10435 [Conf]
    
71. Jurjen Westra, Dirk-Jan Jongeneel, Ralph H. J. M. Otten, Chandu Visweswariah
    Time Budgeting in a Wireplanning Context. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10436-10441 [Conf]
    
72. Ruibing Lu, Cheng-Kok Koh
    Interconnect Planning with Local Area Constrained Retiming. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10442-10447 [Conf]
    
73. Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Muddu
    A Novel Metric for Interconnect Architecture Performance. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10448-10455 [Conf]
    
74. Jianwen Zhu, Wai Sum Mong
    Specification of Non-Functional Intellectual Property Components. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10456-10461 [Conf]
    
75. Yuan Xie, Wayne Wolf, Haris Lekatsas
    Profile-Driven Selective Code Compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10462-10467 [Conf]
    
76. Chengzhi Pan, Nader Bagherzadeh, Amir Hosein Kamalizad, Arezou Koohi
    Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10468-10475 [Conf]
    
77. Wolfgang Rosenstiel, Rudy Lauwereins, Ivo Bolsens, Chris Rowen, Yankin Tanurhan, Kees A. Vissers, S. Wang
    Panel Title: Reconfigurable Computing - Different Perspectives. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10476-10477 [Conf]
    
78. Doris Lupea, Udo Pursche, Hans-Joachim Jentschel
    RF-BIST: Loopback Spectral Signature Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10478-10483 [Conf]
    
79. Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter
    Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10484-10489 [Conf]
    
80. Sujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti
    On Modeling Cross-Talk Faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10490-10495 [Conf]
    
81. Martin John Burbidge, Jim Tijou, Andrew Richardson
    Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loops. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10496-10503 [Conf]
    
82. Venkata Syam P. Rapaka, Diana Marculescu
    Pre-Characterization Free, Efficient Power/Performance Analysis of Embedded and General Purpose Software Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10504-10509 [Conf]
    
83. Mahmut T. Kandemir, Wei Zhang 0002, Mustafa Karaköy
    Runtime Code Parallelization for On-Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10510-10515 [Conf]
    
84. Paul Marchal, José Ignacio Gómez, Luis Piñuel, Davide Bruni, Luca Benini, Francky Catthoor, Henk Corporaal
    SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10516-10523 [Conf]
    
85. Ferran Martorell, Diego Mateo, Xavier Aragonès
    Modeling and Evaluation of Substrate Noise Induced by Interconnects. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10524-10529 [Conf]
    
86. Makram M. Mansour, Amit Mehrotra
    Model-Order Reduction Based on PRONY's Method. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10530-10535 [Conf]
    
87. Stefano Grivet-Talocia, Igor S. Stievano, Ivan A. Maio, Flavio G. Canavero
    Combined FDTD/Macromodel Simulation of Interconnected Digital Devices. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10536-10541 [Conf]
    
88. Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne Wolf
    Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10542-10549 [Conf]
    
89. Sungjoo Yoo, Iuliana Bacivarov, Aimen Bouchhima, Yanick Paviot, Ahmed Amine Jerraya
    Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10550-10555 [Conf]
    
90. Wei Qin, Sharad Malik
    Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10556-10561 [Conf]
    
91. Jürgen Schnerr, Gunter Haug, Wolfgang Rosenstiel
    Instruction Set Emulation for Rapid Prototyping of SoCs . [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10562-10569 [Conf]
    
92. Alberto La Rosa, Luciano Lavagno, Claudio Passerone
    Hardware/Software Design Space Exploration for a Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10570-10575 [Conf]
    
93. João M. P. Cardoso, Markus Weinhardt
    From C Programs to the Configure-Execute Model. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10576-10581 [Conf]
    
94. Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Nicola Mazzocca
    FPGA-Based Implementation of a Serial RSA Processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10582-10589 [Conf]
    
95. Michael Nicolaidis, Nadir Achouri, Slimane Boutobza
    Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10590-10595 [Conf]
    
96. Petros Oikonomakos, Mark Zwolinski, Bashir M. Al-Hashimi
    Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10596-10601 [Conf]
    
97. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10602-10607 [Conf]
    
98. Martin Omaña, Daniele Rossi, Cecilia Metra
    High Speed and Highly Testable Parallel Two-Rail Code Checker. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10608-10615 [Conf]
    
99. Ken Tindell, Hermann Kopetz, Fabian Wolf, Rolf Ernst
    Safe Automotive Software Development. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10616-10623 [Conf]
    
100. Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay
     Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10624-10629 [Conf]
     
101. Carsten Wegener, Michael Peter Kennedy
     Linear Model-Based Error Identification and Calibration for Data Converters. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10630-10635 [Conf]
     
102. Miquel Albiol, José Luis González, Eduard Alarcón
     Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10636-10641 [Conf]
     
103. Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
     Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10642-10649 [Conf]
     
104. Arijit Ghosh, Tony Givargis
     Analytical Design Space Exploration of Caches for Embedded Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10650-10655 [Conf]
     
105. Vladimir D. Zivkovic, Erwin A. de Kock, Pieter van der Wolf, Ed F. Deprettere
     Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10656-10661 [Conf]
     
106. Laura Vanzago, Bishnupriya Bhattacharya, Joel Cambonie, Luciano Lavagno
     Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10662-10667 [Conf]
     
107. William Fornaciari, P. Micheli, Fabio Salice, L. Zampella
     A First Step Towards Hw/Sw Partitioning of UML Specifications. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10668-10673 [Conf]
     
108. Yannick Le Moullec, Nahla Ben Amor, Jean-Philippe Diguet, Mohamed Abid, Jean Luc Philippe
     Multi-Granularity Metrics for the Era of Strongly Personalized SOCs. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10674-10681 [Conf]
     
109. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
     Energy Estimation for Extensible Processors. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10682-10687 [Conf]
     
110. Jingcao Hu, Radu Marculescu
     Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10688-10693 [Conf]
     
111. Wei-Chung Cheng, Massoud Pedram
     Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10694-10699 [Conf]
     
112. Hunsoo Choo, Khurram Muhammad, Kaushik Roy
     MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10700-10705 [Conf]
     
113. Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi
     Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10706-10713 [Conf]
     
114. Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
     Low-Cost Software-Based Self-Testing of RISC Processor Cores. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10714-10719 [Conf]
     
115. Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
     A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10720-10725 [Conf]
     
116. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
     Test Data Compression: The System Integrator's Perspective. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10726-10731 [Conf]
     
117. Zahra Sadat Ebadi, André Ivanov
     Time Domain Multiplexed TAM: Implementation and Comparison. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10732-10737 [Conf]
     
118. Sandeep Kumar Goel, Erik Jan Marinissen
     Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10738-10741 [Conf]
     
119. Qiang Xu, Nicola Nicolici
     Delay Fault Testing of Core-Based Systems-on-a-Chi. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10744-10752 [Conf]
     
120. Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
     Reducing Multi-Valued Algebraic Operations to Binary. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10752-10757 [Conf]
     
121. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
     Combination of Lower Bounds in Exact BDD Minimization. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10758-10763 [Conf]
     
122. Ana T. Freitas, Arlindo L. Oliveira
     Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits: An Application in Power Estimation. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10764-10769 [Conf]
     
123. Ulrich Seidl, Klaus Eckl, Frank M. Johannes
     Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10770-10777 [Conf]
     
124. Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
     Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10778-10783 [Conf]
     
125. G. Surendra, Subhasis Banerjee, S. K. Nandy
     Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10784-10789 [Conf]
     
126. Tudor Dumitras, Radu Marculescu
     On-Chip Stochastic Communication. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10790-10795 [Conf]
     
127. Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhary, Ismail Kadayif
     An Integrated Approach for Improving Cache Behavior. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10796-10801 [Conf]
     
128. Newton Cheung, Jörg Henkel, Sri Parameswaran
     Rapid Configuration and Instruction Selection for an ASIP: A Case Study. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10802-10809 [Conf]
     
129. Yakov Novikov
     Local Search for Boolean Relations on the Basis of Unit Propagation. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10810-10815 [Conf]
     
130. Amit Goel, Randal E. Bryant
     Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10816-10821 [Conf]
     
131. Shuo Sheng, Michael S. Hsiao
     Efficient Preimage Computation Using A Novel Success-Driven ATPG. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10822-10827 [Conf]
     
132. Abhik Roychoudhury, Tulika Mitra, S. R. Karri
     Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10828-10833 [Conf]
     
133. Avi Ziv
     Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions . [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10834-10841 [Conf]
     
134. Reimund Wittmann, Jürgen Hartung, Hans-Joachim Wassener, Günther Tränkle, Michael Schröter
     Hot Topic Session: RF Design Technology for Highly Integrated Communication Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10842-10849 [Conf]
     
135. Kai Wang, Malgorzata Marek-Sadowska
     Power/Ground Mesh Area Optimization Using Multigrid-Based Technique. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10850-10855 [Conf]
     
136. Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu
     A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10856-10861 [Conf]
     
137. Ryon M. Smey, Bill Swartz, Patrick H. Madden
     Crosstalk Reduction in Area Routing. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10862-10867 [Conf]
     
138. Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng
     Area Fill Generation With Inherent Data Volume Reduction. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10868-10875 [Conf]
     
139. Heinz-Joseph Schlebusch, Gary Smith, Donatella Sciuto, Daniel Gajski, Carsten Mielenz, Christopher K. Lennard, Frank Ghenassia, Stuart Swan, Joachim Kunkel
     Transaction Based Design: Another Buzzword or the Solution to a Design Problem? [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10876-10879 [Conf]
     
140. Lintao Zhang, Sharad Malik
     Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10880-10885 [Conf]
     
141. Evguenii I. Goldberg, Yakov Novikov
     Verification of Proofs of Unsatisfiability for CNF Formulas. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10886-10891 [Conf]
     
142. Feng Lu, Li-C. Wang, Kwang-Ting Cheng, Ric C.-Y. Huang
     A Circuit SAT Solver With Signal Correlation Guided Learning. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10892-10897 [Conf]
     
143. Gianpiero Cabodi, Sergio Nocco, Stefano Quer
     Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10898-10905 [Conf]
     
144. Victor De La Luz, Mahmut T. Kandemir, Ismail Kadayif, Ugur Sezer
     Generalized Data Transformations for Enhancing Cache Behavior. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10906-10911 [Conf]
     
145. Pramote Kuacharoen, Vincent John Mooney, Vijay K. Madisetti
     Software Streaming via Block Streaming. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10912-10917 [Conf]
     
146. Ying Zhang, Krishnendu Chakrabarty
     Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10918-10925 [Conf]
     
147. Agnes Madalinski, Alexandre V. Bystrov, Victor Khomenko, Alexandre Yakovlev
     Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10926-10931 [Conf]
     
148. Danil Sokolov, Alexandre V. Bystrov, Alexandre Yakovlev
     STG Optimisation in the Direct Mapping of Asynchronous Circuits . [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10932-10939 [Conf]
     
149. Leandro Soares Indrusiak, Florian Lubitz, Ricardo Augusto da Luz Reis, Manfred Glesner
     Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10940-10945 [Conf]
     
150. Wolfgang Müller 0003, Tim Schattkowsky, Heinz-Josef Eikerling, Jan Wegner
     Dynamic Tool Integration in Heterogeneous Computer Networks. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10946-10953 [Conf]
     
151. Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas
     Layered, Multi-Threaded, High-Level Performance Design. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10954-10959 [Conf]
     
152. Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
     A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10960-10965 [Conf]
     
153. Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl
     Processor/Memory Co-Exploration on Multiple Abstraction Levels. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10966-10973 [Conf]
     
154. Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira
     Run-Time Management of Logic Resources on Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10974-10979 [Conf]
     
155. Michael Dales
     Managing a Reconfigurable Processor in a General Purpose Workstation Environment. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10980-10985 [Conf]
     
156. Jean-Yves Mignolet, Vincent Nollet, Paul Coene, Diederik Verkest, Serge Vernalde, Rudy Lauwereins
     Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10986-10993 [Conf]
     
157. Marcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira
     RTL Test Pattern Generation for High Quality Loosely Deterministic BIST. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:10994-10999 [Conf]
     
158. Irith Pomeranz, Sudhakar M. Reddy
     A New Approach to Test Generation and Test Compaction for Scan Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11000-11005 [Conf]
     
159. Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
     Fully Automatic Test Program Generation for Microprocessor Cores. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11006-11011 [Conf]
     
160. Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
     On the Characterization of Hard-to-Detect Bridging Faults. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11012-11019 [Conf]
     
161. Yu-Min Lee, Charlie Chung-Ping Chen
     The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method . [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11020-11025 [Conf]
     
162. Zhong Wang, Jianwen Zhu
     Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11026-11031 [Conf]
     
163. Márta Rencz, Vladimir Székely, A. Poppe
     A Fast Algorithm for the Layout Based Electro-Thermal Simulation. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11032-11037 [Conf]
     
164. Renate Henftling, Andreas Zinn, Matthias Bauer, Wolfgang Ecker, Martin Zambaldi
     Platform-Based Testbench Generation. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11038-11045 [Conf]
     
165. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
     Software Architectural Transformations: A New Approach to Low Energy Embedded Software. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11046-11051 [Conf]
     
166. Steve Haga, Natasha Reeves, Rajeev Barua, Diana Marculescu
     Dynamic Functional Unit Assignment for Low Power. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11052-11057 [Conf]
     
167. Mahmut T. Kandemir, Ibrahim Kolcu, Wei Zhang 0002
     Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11058-11063 [Conf]
     
168. Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau
     Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11064-11069 [Conf]
     
169. Erik Brockmeyer, Miguel Miranda, Henk Corporaal, Francky Catthoor
     Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11070-11075 [Conf]
     
170. Sambuddhi Hettiaratchi, Peter Y. K. Cheung
     Mesh Partitioning Approach to Energy Efficient Data Layout. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11076-11081 [Conf]
     
171. Mahesh Mamidipaka, Nikil D. Dutt
     On-chip Stack Based Memory Organization for Low Power Embedded Architectures. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11082-11089 [Conf]
     
172. Martin Vogels, Georges G. E. Gielen
     Figure of Merit Based Selection of A/D Converters. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11090-11091 [Conf]
     
173. Oliver Kraus, Martin Padeffke
     XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11092-11093 [Conf]
     
174. Johnson S. Kin, José Luis Pino
     Multithreaded Synchronous Data Flow Simulation. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11094-11095 [Conf]
     
175. Kenneth Fazel, Mitchell A. Thornton, Robert B. Reese
     PLFire: A Visualization Tool for Asynchronous Phased Logic Designs. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11096-11097 [Conf]
     
176. Simona Doboli, Gaurav Gothoskar, Alex Doboli
     Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11098-11099 [Conf]
     
177. Abhijit K. Deb, Johnny Öberg, Axel Jantsch
     Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11100-11101 [Conf]
     
178. Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang
     A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11102-11103 [Conf]
     
179. Wonjoon Choi, Kia Bazargan
     Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11104-11105 [Conf]
     
180. Alessandro Girardi, Sergio Bampi
     LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11106-11107 [Conf]
     
181. Alicia Manthe, Zhao Li, C.-J. Richard Shi, Kartikeya Mayaram
     Symbolic Analysis of Nonlinear Analog Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11108-11109 [Conf]
     
182. Jens Gerling, Oliver Stübbe, Jürgen Schrage, Gerd Mrozynski, Jürgen Teich
     Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11110-11111 [Conf]
     
183. Seung Hoon Choi, Kaushik Roy
     A New Crosstalk Noise Model for DOMINO Logic Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11112-11113 [Conf]
     
184. Li Ding 0002, Pinaki Mazumder
     Modeling Noise Transfer Characteristic of Dynamic Logic Gates. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11114-11117 [Conf]
     
185. Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit
     Heterogeneous Programmable Logic Block Architectures. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11118-11119 [Conf]
     
186. Jürgen Becker, Alexander Thomas, Martin Vorbach, Volker Baumgarten
     An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11120-11121 [Conf]
     
187. Fernando Gehm Moraes, Daniel Mesquita, José Carlos S. Palma, Leandro Möller, Ney Laert Vilar Calazans
     Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11122-11123 [Conf]
     
188. Michèl A. J. Rosien, Yuanqing Guo, Gerard J. M. Smit, Thijs Krol
     Mapping Applications to an FPFA Tile. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11124-11125 [Conf]
     
189. Erland Nilsson, Mikael Millberg, Johnny Öberg, Axel Jantsch
     Load Distribution with the Proximity Congestion Awareness in a Network on Chip. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11126-11127 [Conf]
     
190. Adrijean Andriahantenaina, Alain Greiner
     Micro-Network for SoC: Implementation of a 32-Port SPIN network. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11128-11129 [Conf]
     
191. Achim Rettberg, Mauro Cesar Zanella, Christophe Bobda, Thomas Lehmann
     A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11130-11131 [Conf]
     
192. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
     Library Functions Timing Characterization for Source-Level Analysis. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11132-11133 [Conf]
     
193. Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang
     G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11134-11135 [Conf]
     
194. S. F. Nielsen, Jan Madsen
     Power Constrained High-Level Synthesis of Battery Powered Digital Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11136-11137 [Conf]
     
195. Bilge Saglam Akgul, Vincent John Mooney III
     PARLAK: Parametrized Lock Cache Generator. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11138-11139 [Conf]
     
196. Tom J. Kazmierski, Xing Q. Yang
     A Secure Web-Based Framework for Electronic System Level Design. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11140-11143 [Conf]
     
197. Pieter Op de Beeck, C. Ghez, Erik Brockmeyer, Miguel Miranda, Francky Catthoor, Geert Deconinck
     Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11144-11145 [Conf]
     
198. Wei Zhang 0002, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De
     Compiler Support for Reducing Leakage Energy Consumption. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11146-11147 [Conf]
     
199. Peng Rong, Massoud Pedram
     An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11148-11149 [Conf]
     
200. Jiong Luo, Li-Shiuan Peh, Niraj K. Jha
     Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11150-11151 [Conf]
     
201. MingHung Lee, TingTing Hwang, Shi-Yu Huang
     Decomposition of Extended Finite State Machine for Low Power Design. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11152-11153 [Conf]
     
202. Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli
     Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11154-11155 [Conf]
     
203. Markus Wedler, Dominik Stoffel, Wolfgang Kunz
     Using RTL Statespace Information and State Encoding for Induction Based Property Checking. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11156-11157 [Conf]
     
204. Enric Pastor, Marco A. Peña
     Combining Simulation and Guided Traversal for the Verification of Concurrent Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11158-11159 [Conf]
     
205. Naran Sirisantana, Kaushik Roy
     Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11160-11161 [Conf]
     
206. Steffen Tarnick
     Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden Codes. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11162-11163 [Conf]
     
207. Petros Drineas, Yiorgos Makris
     Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11164-11167 [Conf]
     
208. Christian Haubelt, Jürgen Teich, Rainer Feldmann, Burkhard Monien
     SAT-Based Techniques in System Synthesis. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11168-11169 [Conf]
     
209. Christoph Grimm, Christian Meise, Wilhelm Heupke, Klaus Waldschmidt
     Refinement of Mixed-Signal Systems with SystemC. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11170-11171 [Conf]
     
210. Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh K. Gupta, Frederic Doucet
     Polychrony for Refinement-Based Design. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11172-11173 [Conf]
     
211. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
     Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11174-11175 [Conf]
     
212. Ivo Schanstra, A. J. van de Goor
     Consequences of RAM Bitline Twisting for Test Coverage. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11176-11177 [Conf]
     
213. Francesco Corsi, Cristoforo Marzocca, Gianvito Matarrese
     An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing Scheme. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11178-11179 [Conf]
     
214. Hideyuki Ichihara, Tomoo Inoue
     Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11180-11181 [Conf]
     
215. Ondrej Novák
     Comparison of Test Pattern Decompression Techniques. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11182-11183 [Conf]
     
216. Ilia Polian, Bernd Becker, Sudhakar M. Reddy
     Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11184-11185 [Conf]
     
217. Irith Pomeranz, Sudhakar M. Reddy
     Test Data Compression Based on Output Dependence. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11186-11187 [Conf]
     
218. Vikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty
     A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:11188-11190 [Conf]
     
219. Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo
     Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20002-20007 [Conf]
     
220. Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klußmann, Peter Pirsch
     HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20008-20013 [Conf]
     
221. G. Lykakis, N. Mouratidis, Kyriakos Vlachos, Nikos A. Nikolaou, Stylianos Perissakis, G. Sourdis, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Dionisios I. Reisis
     Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20014-20019 [Conf]
     
222. Alex Panato, Marcelo Barcelos, Ricardo Augusto da Luz Reis
     A Low Device Occupation IP to Implement Rijndael Algorithm. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20020-20025 [Conf]
     
223. Marco Caldari, Massimo Conti, Massimo Coppola, Stephane Curaba, Lorenzo Pieralisi, Claudio Turchetti
     Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20026-20031 [Conf]
     
224. Marco Caldari, Massimo Conti, Massimo Coppola, Paolo Crippa, Simone Orcioni, Lorenzo Pieralisi, Claudio Turchetti
     System-Level Power Analysis Methodology Applied to the AMBA AHB Bus. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20032-20039 [Conf]
     
225. S. Glaeson, E. Petit
     Designing System-Level Software Solutions for Open OS's on 3g Wireless Handsets. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20040- [Conf]
     
226. Monica Besana, Michele Borgatti
     Application Mapping to a Hardware Platform through Automated Code Generation Targeting a RTOS: A Design Case Study. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20041-20044 [Conf]
     
227. Marek Jersak, Kai Richter, Rolf Ernst, Jörn-Christian Braam, Zheng-Yu Jiang, Fabian Wolf
     Formal Methods for Integration of Automotive Software. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20045-20050 [Conf]
     
228. Frédéric Pétrot, Pascal Gomez
     Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20051-20056 [Conf]
     
229. B. Nicolescu, Raoul Velazco
     Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20057-20063 [Conf]
     
230. Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane
     Network Processing Challenges and an Experimental NPU Platform. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20064-20069 [Conf]
     
231. Adrijean Andriahantenaina, Hervé Charlery, Alain Greiner, Laurent Mortiez, Cesar Albenes Zeferino
     SPIN: A Scalable, Packet Switched, On-Chip Micro-Network. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20070-20073 [Conf]
     
232. Naresh Soni, Nick Richardson, Lun Bin Huang, Suresh Rajgopal, George Vlantis
     NPSE: A High Performance Network Packet Search Engine. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20074-20081 [Conf]
     
233. Koji Ara, Kei Suzuki
     A Proposal for Transaction-Level Verification with Component Wrapper Language. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20082-20087 [Conf]
     
234. Franco Carbognani, Christopher K. Lennard, C. Norris Ip, Allan Cochrane, Paul Bates
     Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20088-20094 [Conf]
     
235. Ali Sayinta, Gorkem Canverdi, Marc Pauwels, Amer Alshawa, Wim Dehaene
     A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20095-20100 [Conf]
     
236. Massimo Bombana, Francesco Bruschi
     SystemC-VHDL Co-Simulation and Synthesis in the HW Domain. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20101-20105 [Conf]
     
237. Marcello Coppola, Stephane Curaba, Miltos D. Grammatikakis, Giuseppe Maruccia
     IPSIM: SystemC 3.0 Enhancements for Communication Refinement. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20106-20111 [Conf]
     
238. Francesco Bruschi, Fabrizio Ferrandi
     Synthesis of Complex Control Structures from Behavioral SystemC Models. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20112-20119 [Conf]
     
239. Imed Moussa, Thierry Grellier, Giang Nguyen
     Exploring SW Performance Using SoC Transaction-Level Modeling. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20120-20125 [Conf]
     
240. Marco Göltze
     A Flexible Object-Oriented Software Architecture for Smart Wireless Communication Devices. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20126-20131 [Conf]
     
241. Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh
     Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20132-20137 [Conf]
     
242. Shinya Honda, Hiroaki Takada
     Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20138-20143 [Conf]
     
243. Haitao Du, Marcos Sanchez-Elez, Nozar Tabrizi, Nader Bagherzadeh, Manuel L. Anido, Milagros Fernández
     Interactive Ray Tracing on Reconfigurable SIMD MorphoSys. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20144-20149 [Conf]
     
244. Stephen Jan, Paolo de Dios, Stephen A. Edwards
     Porting a Network Cryptographic Service to the RMC2000: A Case Study in Embedded Software Development. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20150-20157 [Conf]
     
245. Johan Lilius, Dragos Truscan, Seppo Virtanen
     Fast Evaluation of Protocol Processor Architectures for IPv6 Routing. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20158-20163 [Conf]
     
246. Silvia Brini, Doha Benjelloun, Fabien Castanier
     A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20164-20169 [Conf]
     
247. Sharath Kodase, Shige Wang, Kang G. Shin
     Transforming Structural Model to Runtime Model of Embedded Software with Real-Time Constraints. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20170-20175 [Conf]
     
248. Osamu Ogawa, Sylvain Bayon de Noyer, Pascal Chauvet, Katsuya Shinohara, Yoshiharu Watanabe, Hiroshi Niizuma, Takayuki Sasaki, Yuji Takai
     A Practical Approach for Bus Architecture Optimization at Transaction Level. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20176-20181 [Conf]
     
249. Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria
     Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20182-20187 [Conf]
     
250. Nicola Drago, Franco Fummi, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino
     Estimation of Bus Performance for a Tuplespace in an Embedded Architecture. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20188-20195 [Conf]
     
251. Árpád Burmen, Janez Puhan, Tadej Tuma
     Defining Cost Functions for Robust IC Design and Optimization. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20196-20201 [Conf]
     
252. Martin Schrader, Roderick McConnell
     SoC Design and Test Considerations. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20202-20207 [Conf]
     
253. Bernard Laurent, Thierry Karger
     A System to Validate and Certify Soft and Hard IP. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20208-20213 [Conf]
     
254. Marco Caldari, Massimo Conti, Paolo Crippa, Giuliano Marozzi, Fabio Di Gennaro, Simone Orcioni, Claudio Turchetti
     SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20214-20219 [Conf]
     
255. François Rémond, Pierre Bricaud
     Set Top Box SoC Design Methodology at STMicroelectronics. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20220-20223 [Conf]
     
256. Fotis Andritsopoulos, C. Charopoulos, Gregory Doumenis, Fotis Karoubalis, Yannis Mitsos, F. Petreas, Ioanna Theologitou, Stylianos Perissakis, Dionisios I. Reisis
     Verification of a Complex SoC: The PRO3 Case-Study. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20224-20231 [Conf]
     
257. Leonardo Mangeruca, Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli, Andrea Pierantoni, Michele Pennese
     System Level Design of Embedded Controllers: Knock Detection, A Case Study in the Automotive Domain. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20232-20237 [Conf]
     
258. Matjaz Verderber, Andrej Zemva, Damjan Lampret
     HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20238-20243 [Conf]
     
259. Jürgen Helmschmidt, Eberhard Schüler, Prashant Rao, Sergio Rossi, Serge di Matteo, Rainer Bonitz
     Reconfigurable Signal Processing in Wireless Terminals. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20244-20249 [Conf]
     
260. Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Riadh Gaiech, Eric Martin
     A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20250-20255 [Conf]
     
261. Matthias Gries, Chidamber Kulkarni, Christian Sauer, Kurt Keutzer
     Comparing Analytical Modeling with Simulation for Network Processors: A Case Study. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20256-20261 [Conf]
     
262. Alessandro Pirola
     A Solution for Hardware Emulation of Non Volatile Memory Macrocells. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20262-20267 [Conf]
     
263. Rami Ahola, Daniel Wallner, Marius Sida
     Bluetooth Transceiver Design with VHDL-AMS. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20268-20273 [Conf]
     
264. Pierluigi Daglio, Carlo Roma
     A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20274-20279 [Conf]
     
265. Ayman Mounir, Ahmed Mostafa, Maged Fikry
     Automatic Behavioural Model Calibration for Efficient PLL System Verification. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20280-20285 [Conf]
     
266. Uwe Knöchel, Thomas Markwirth, Jürgen Hartung, Ralf Kakerow, Radhakrishna Atukula
     Verification of the RF Subsystem within Wireless LAN System Level Simulation. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20286-20291 [Conf]
     
267. Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger, Richard B. Brown
     A Top-Down Microsystems Design Methodology and Associated Challenges . [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20292-20296 [Conf]
     
268. Ramy Iskander, Mohamed Dessouky, Maie Aly, Mahmoud Magdy, Noha Hassan, Noha Soliman, Sami Moussa
     Synthesis of CMOS Analog Cells Using AMIGO. [Citation Graph (0, 0)][DBLP]
     DATE, 2003, pp:20297-20302 [Conf]