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Frédéric Pétrot :
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Frédéric Pétrot , Denis Hommais , Alain Greiner A Simulation Environment for Core Based Embedded Systems. [Citation Graph (0, 0)][DBLP ] Annual Simulation Symposium, 1997, pp:86-91 [Conf ] Denis Hommais , Frédéric Pétrot , Ivan Augé A practical tool box for system level communication synthesis. [Citation Graph (0, 0)][DBLP ] CODES, 2001, pp:48-53 [Conf ] Jean-Yves Brunel , W. M. Kruijtzer , H. J. H. N. Kenter , Frédéric Pétrot , L. Pasquier , Erwin A. de Kock , W. J. M. Smits COSY communication IP's. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:406-409 [Conf ] Ahmed Amine Jerraya , Aimen Bouchhima , Frédéric Pétrot Programming models and HW-SW interfaces abstraction for multi-processor SoC. [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:280-285 [Conf ] Frédéric Pétrot , Pascal Gomez Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:20051-20056 [Conf ] Frédéric Pétrot , Alain Greiner , Pascal Gomez On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures. [Citation Graph (0, 0)][DBLP ] DSD, 2006, pp:53-60 [Conf ] Aimen Bouchhima , Xi Chen , Frédéric Pétrot , Wander O. Cesário , Ahmed Amine Jerraya A unified HW/SW interface model to remove discontinuities between HW and SW design. [Citation Graph (0, 0)][DBLP ] EMSOFT, 2005, pp:159-163 [Conf ] Ludovic Jacomme , Frédéric Pétrot , Rajesh K. Bawa Formal Extraction of Memorizing Elements for Sequential VHDL Synthesis. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1998, pp:10317-10620 [Conf ] Denis Hommais , Frédéric Pétrot Efficient Combinational Loops Handling for Cycle Precise Simulation of System on a Chip. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1998, pp:10051-10054 [Conf ] Frédéric Pétrot , Denis Hommais , Alain Greiner Cycle precise core based hardware/software system simulation with predictable event propagation. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1997, pp:182-187 [Conf ] Saifeddine Berrayana , Etienne Faure , Daniela Genius , Frédéric Pétrot Modular On-chip Multiprocessor for Routing Applications. [Citation Graph (0, 0)][DBLP ] Euro-Par, 2004, pp:846-855 [Conf ] Marcello Duhalde , Alain Greiner , Frédéric Pétrot A High Performance Modular Embedded ROM Architecture. [Citation Graph (0, 0)][DBLP ] ISCAS, 1995, pp:1057-1060 [Conf ] Alain Greiner , Frédéric Pétrot , M. Carrier , Mounir Benabdenbi , R. Chotin-Avot , Raphaël Labayrade MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation. [Citation Graph (0, 0)][DBLP ] ReCoSoC, 2006, pp:24-30 [Conf ] Denis Hommais , Frédéric Pétrot , Ivan Augé A Tool Box to Map System Level Communications on HW/SW Architectures. [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 2001, pp:77-83 [Conf ] Lobna Kriaa , Aimen Bouchhima , Wassim Youssef , Frédéric Pétrot , Anne-Marie Fouillart , Ahmed Amine Jerraya Service Based Component Design Approach for Flexible Hardware/Software Interface Modeling. [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 2006, pp:156-162 [Conf ] Benaoumeur Senouci , Aimen Bouchhima , Frédéric Rousseau , Frédéric Pétrot , Ahmed Amine Jerraya Fast Prototyping of POSIX Based Applications on a Multiprocessor SoC Architecture: "Hardware-Dependent Software Oriented Approach". [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 2006, pp:69-75 [Conf ] Ivan Augé , François Donnet , Frédéric Pétrot Retiming Finite State Machines to Control Hardened Data-Paths. [Citation Graph (0, 0)][DBLP ] SBCCI, 2003, pp:41-46 [Conf ] Ludovic Jacomme , Frédéric Pétrot , Rajesh K. Bawa Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1999, pp:151-156 [Conf ] Ivan Augé , Frédéric Pétrot , François Donnet , Pascal Gomez Platform-based design from parallel C specifications. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1811-1826 [Journal ] Scalable Multi-FPGA Platform for Networks-On-Chip Emulation. [Citation Graph (, )][DBLP ] A System Framework for the Design of Embedded Software Targeting Heterogeneous Multi-core SoCs. [Citation Graph (, )][DBLP ] Automatic instrumentation of embedded software for high level hardware/software co-simulation. [Citation Graph (, )][DBLP ] Novel task migration framework on configurable heterogeneous MPSoC platforms. [Citation Graph (, )][DBLP ] Using binary translation in event driven simulation for fast and flexible MPSoC simulation. [Citation Graph (, )][DBLP ] Native MPSoC co-simulation environment for software performance estimation. [Citation Graph (, )][DBLP ] Efficient Implementation of Native Software Simulation for MPSoC. [Citation Graph (, )][DBLP ] Comparison of memory write policies for NoC based Multicore Cache Coherent Systems. [Citation Graph (, )][DBLP ] Extending IP-XACT to support an MDE based approach for SoC design. [Citation Graph (, )][DBLP ] Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform. [Citation Graph (, )][DBLP ] Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture. [Citation Graph (, )][DBLP ] Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation. [Citation Graph (, )][DBLP ] A MPSoC Prototyping Platform for Flexible Radio Applications. [Citation Graph (, )][DBLP ] Using C to write portable CMOS VLSI module generators. [Citation Graph (, )][DBLP ] Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform. [Citation Graph (, )][DBLP ] Multi-CPU/FPGA Platform Based Heterogeneous Multiprocessor Prototyping: New Challenges for Embedded Software Designers. [Citation Graph (, )][DBLP ] Synthesis of Communication Mechanisms for Multi-tile Systems Based on Heterogeneous Multi-processor System-On-Chips. [Citation Graph (, )][DBLP ] Configurable Heterogeneous MPSoC Architecture Exploration Using Abstraction Levels. [Citation Graph (, )][DBLP ] An intermediate format for automatic generation of MPSoC virtual prototypes. [Citation Graph (, )][DBLP ] MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method. [Citation Graph (, )][DBLP ] Modelling and architecture exploration of a medium voltage protection device. [Citation Graph (, )][DBLP ] Prototyping Multiprocessor System-on-Chip Applications: A Platform-Based Approach. [Citation Graph (, )][DBLP ] Search in 0.032secs, Finished in 0.035secs