Conferences in DBLP
(recosoc) Claudio Brunelli , Fabio Garzia , Jari Nurmi A Coarse-Grain Reconfigurable Machine with Floating-Point Arithmetic Capabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Warkentin , Florian Dittmann Data Transfer Protocols for a Two Slot Based Reconfigurable Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Timo Vogt , Christian Neeb , Norbert Wehn A Reconfigurable Multi-Processor Platform for Convolutional and Turbo Decoding. [Citation Graph (0, 0)][DBLP ] Conf ] Alain Greiner , Frédéric Pétrot , M. Carrier , Mounir Benabdenbi , R. Chotin-Avot , Raphaël Labayrade MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation. [Citation Graph (0, 0)][DBLP ] Conf ] Dmitrij Kissler , Frank Hannig , Alexey Kupriyanov , Jürgen Teich A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Gallini , Alberto Rosti , Sara Bocchio Compilation Techniques for Configurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Morra , M. Sackmann , Jürgen Becker , Reiner W. Hartenstein Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Nicolas Valette , Lionel Torres , Gilles Sassatelli , S. Bancel How to Secure Embedded Programmable Gate Arrays? [Citation Graph (0, 0)][DBLP ] Conf ] Romain Vaslin , Guy Gogniat , Jean-Philippe Diguet Secure Architecture in Embedded Systems: an Overview. [Citation Graph (0, 0)][DBLP ] Conf ] Reouven Elbaz , Lionel Torres , Gilles Sassatelli , Pierre Guillemin , Michel Bardouillet , Albert Martinez Efficient Combination of Data Encryption and Integrity Checking for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Sill , Claas Cornelius , Stephan Kubisch , Dirk Timmermann Mixed Gates: Leakage Reduction techniques applied to Switches for Networks-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Senn , Nathalie Julien , David Elléouet , Yannig Savary , Nabil Abdelli Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA Design. [Citation Graph (0, 0)][DBLP ] Conf ] Yana Esteves Krasteva , Eduardo de la Torre , Teresa Riesgo Partial Reconfiguration for Core Reallocation and Flexible Communications. [Citation Graph (0, 0)][DBLP ] Conf ] Nicolas Abel , Lounis Kessal , Sébastien Pillement , Didier Demigny Clear Stream towards Dynamically Reconfigurable Systems on Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Heiko Hinkelmann , Peter Zipf , Manfred Glesner A Concept for a Profile-based Dynamic Reconfiguration Mechanism. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Kühn , Felix Madlener , Sorin A. Huss Resource Management for Dynamic Reconfigurable Hardware Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Hayder Mrabet , Zied Marrakchi , Pierre Souillot , Habib Mehrez , André Tissot Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Nicolas Bruchon , Lionel Torres , Gilles Sassatelli , Gaston Cambon Remanent SRAM Structure for Runtime Reconfigurable FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Grégory Gailliard , Bertrand Mercier , Michel Sarlotte , Bernard Candaele , François Verdier Towards a SystemC TLM based Methodology for Platform Design and IP Reuse: Application to Software Defined Radio. [Citation Graph (0, 0)][DBLP ] Conf ] C. A. DeJuan-Esteban , A. Rosado-Muñoz , Emilio Soria-Olivas , M. Bataller-Mompeán , Juan Guerrero-Martínez An approach to Co-design of Complex Adaptive Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Gert Jervan , Anton Arhipov , Peeter Ellervee Work in Progress: FPGA Based Emulation Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Erwan Piriou , Christophe Jégo , Patrick Adde , Michel Jézéquel Design, Implementation and Prototyping of a Flexible Architecture Dedicated to Block Turbo Decoding. [Citation Graph (0, 0)][DBLP ] Conf ] Hua Zhong , Leandro Soares Indrusiak , Heiko Hinkelmann , Manfred Glesner Exploring Functional Unit Parallelism in Reconfigurable Computing Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Stéphane Chevobbe , Raphaël David , Frédéric Blanc , Thierry Collette , Olivier Sentieys Control Unit for Parallel Embedded System. [Citation Graph (0, 0)][DBLP ] Conf ] Jerome Dubois , Dominique Ginhac , Michel Paindavoine Design of a 10000 Frames/s CMOS Sensor with In Situ Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt Franz Ackermann , Friedhelm Mayer , Leandro Soares Indrusiak , Manfred Glesner Adaptable Image Processing System based on FPGA Modular Multi Kernel Instantiations. [Citation Graph (0, 0)][DBLP ] Conf ] Barthélémy Heyrman , Michel Paindavoine SystemC design of a smart camera. [Citation Graph (0, 0)][DBLP ] Conf ] D. Puschini , Fabien Clermidy A Comparison between NoC and Bus Architectures Based on a Real-Application. [Citation Graph (0, 0)][DBLP ] Conf ] Vincent Brost , Fan Yang , Michel Paindavoine Embedded System Prototyping Experience Using Multi-DSPs VHDL Model. [Citation Graph (0, 0)][DBLP ] Conf ] J. Khan , Y. Elhillali , S. Niar , A. Rivenq A Low Speed Digital Correlator Architecture Optimized For Resource Savings. [Citation Graph (0, 0)][DBLP ] Conf ] Pascal Manet , Jean-Baptiste Rigaud , Julien Francq , Marc Jeambrun , Assia Tria , Bruno Robisson , Jerome Quartana , Selma Laabidi Integrated Evaluation Platform for Secured Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Benoît Badrignans , Daniel Mesquita , Jean-Claude Bajard , Lionel Torres , Gilles Sassatelli , Michel Robert A Parallel and Secure Architecture for Asymmetric Cryptography. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Borgosz FPGA Implementation of a Digital Jitter Measurement Method for SDH Data Streams. [Citation Graph (0, 0)][DBLP ] Conf ] Yaseer A. Durrani , Teresa Riesgo Power Macromodeling for High Level Power Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Etienne Faure , Alain Greiner , Daniela Genius A generic hardware/software communication mechanism for Multi-Processor System on Chip, Targeting Telecommunication Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Viktor Fischer , Lionel Torres , Daniel Mesquita Flexible security and its technology limits. [Citation Graph (0, 0)][DBLP ] Conf ] 