Conferences in DBLP
Giovanni Chiola Some Research Projects on Clusters of Personal Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Michael R. Lyu Keynote Speech: Design Testing and Evaluation Techniques for Software Reliability Engineering. [Citation Graph (0, 0)][DBLP ] Conf ] Lech Józwiak , Niek Ederveen , Adam Postula Solving Synthesis Problems with Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Mariusz Rawski , Tadeusz Luba , Lech Józwiak , Artur Chojnacki Efficient Logic Synthesis for FPGAs with Functional Decomposition Based on Information Relationship Measure. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Burns , Marek A. Perkowski , Lech Józwiak An Efficient Approach to Decomposition of Multi-Output Boolean Functions with Large Sets of Bound Variables. [Citation Graph (0, 0)][DBLP ] Conf ] Henry Selvaraj , Muthukumar Venkatesan A Reconfiguarable Printed Character Recognition System Using a Logic Synthesis Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Corrie Huijs Design Correctness of Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Blumenröhr , Dirk Eisenbiegler Performing High-Level Synthesis via Program Transformations within a Theorem Prover. [Citation Graph (0, 0)][DBLP ] Conf ] Johnny Öberg , Anshul Kumar , Ahmed Hemani Specification of Exception Handling in Grammar-Based Hardware Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] A. C. Verschueren Rule Base Driven Conversion of an Object Oriented Design Data Structure into Standard Hardware Description Languages. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammed El Shobaki Verification of Embedded Real-Time Systems Using Hardware/Software Cosimulation. [Citation Graph (0, 0)][DBLP ] Conf ] Denis Hommais , Frédéric Pétrot Efficient Combinational Loops Handling for Cycle Precise Simulation of System on a Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Mattias O'Nils , Johnny Öberg , Axel Jantsch Grammar Based Modelling and Synthesis of Device Drivers and Bus Interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Armin Bender Optimal System-Level Synthesis of Digital Systems for Real-Time Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jesper Grode , Jan Madsen A Uni.ed Component Modeling Approach for Performance Estimation in Hardware/Software Codesign. [Citation Graph (0, 0)][DBLP ] Conf ] Joan Aranda , Joan Climent , Antoni Grau A FPGA Implementation of a Video Rate Multi-Target Tracking System. [Citation Graph (0, 0)][DBLP ] Conf ] Krzysztof Kuchcinski An Approach to High-Level Synthesis Using Constraint Logic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Flavius Gruian , Krzysztof Kuchcinski Operation Binding and Scheduling for Low Power Using Constraint Logic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] George Economakos , George K. Papakonstantinou Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Katzalin Olcoz , Francisco Tirado Register Allocation with Simultaneous BIST Intrusio. [Citation Graph (0, 0)][DBLP ] Conf ] Laurence Tianruo Yang , Zebo Peng An Improved Register-Transfer Level Functional Partitioning Approach for Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Postula , Song Chen , Lech Józwiak , David Abramson Automated Synthesis of Interleaved Memory Systems for Custom Computing Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Arrigo Benedetti , Andrea Prati , Nello Scarabottolo Image Convolution on FPGAs: The Implementation of a Multi-FPGA FIFO Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Kazimierz Wiatr Pipeline Architecture of Specialized Reconfigurable Processors in FPGA Structures for Real-Time Image Pre-Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto R. Osorio , Montserrat Bóo , Javier D. Bruguera Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Frédéric Mallet , Fernand Boéri , Jean-François Duboc Hardware Architecture Modelling Using an Object-Oriented Method. [Citation Graph (0, 0)][DBLP ] Conf ] Jeroen Voeten , P. H. A. van der Putten , Marc Geilen , M. P. J. Stevens System Level Modelling for Hardware/Software Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Diego C. Ruspini , Oussama Khatib , Giovanni De Micheli Hardware-Softw are Run-Time Systems and Robotics: A Case Study Vincent John Mooney III. [Citation Graph (0, 0)][DBLP ] Conf ] Petru Eles , Krzysztof Kuchcinski , Zebo Peng , Alexa Doboli , Paul Pop Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Samary Baranov Minimization of Algorithmic State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Dariusz Bojanowicz How Faults can be Simulated in Self-Testable VLSI Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Sosnowski Experimental Evaluation of Pseudorandom Test Effectiveness. [Citation Graph (0, 0)][DBLP ] Conf ] Lilia Kashirova , Olga Tveretina Entropy-Based Design of Low Power FSMs. [Citation Graph (0, 0)][DBLP ] Conf ] Juan de Vicente , Juan Lanchares , Román Hermida RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Igor Lemberski Modified Approach to Automata State Encoding for LUT FPGA Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Valery Sklyarov , Nuno Lau , Ricardo Sal Monteiro , Andreia Melo , Arnaldo Oliveira , Konstantin Kondratjuk Design of Virtual Digital Controllers Based on Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] H.-Ch. Dahmen , Uwe Gläser The Impact of Area Optimization for the Power Consumption of Controllers. [Citation Graph (0, 0)][DBLP ] Conf ] S. Aiello , Antonio Anzalone , M. Bartolucci , G. Cardella , S. Cavallaro , E. De Filippo , S. Femino , C. Garusi , M. Geraci , Francesco Giustolisi , Paolo Guazzoni , M. Iacono Manno , G. Lanzalone , G. Lanzano , S. Lo Nigro , G. Manfredi , A. Pagano , M. Papa , S. Pirrone , G. Politi , F. Porto , F. Rizzo , S. Sambataro , G. Savino , L. Sperduto , C. Sutera , Luisa Zetta Extending a Monoprocessor Real-Time System in a Multiprocessing Environment, DSP-Based. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Chiu-sing Choy , Tin-chak Pang , Juraj Povazanec , Cheong-fat Chan A Useful Micropipeline Architecture to Implement DSP Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] S. Sánchez , Daniel Meziat , M. Carbajo , J. Medina , E. Bronchalo , J. Rodríguez-Pacheco , L. del Pera Control System for a Low Energy Particle Detector. [Citation Graph (0, 0)][DBLP ] Conf ] C. John Glossner , Stamatis Vassiliadis DELFT-JAVA Link Translation Buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Eduard Cerny , Fen Jin Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Youngsoo Shin , Kiyoung Choi Rate Assignment for Embedded Reactive Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander G. Dean , John Paul Shen Hardware to Software Migration with Real-Time Thread Integration. [Citation Graph (0, 0)][DBLP ] Conf ] Loc Bao Nguen , Marek A. Perkowski , Lech Józwiak Design of Self-Synchronized Component FSMs for Self-Timed Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Manfred Koegst , Günter Franke , Steffen Rülke , Klaus Feske Multi-Criterial State Assignment for Low Power FSM Design. [Citation Graph (0, 0)][DBLP ] Conf ] Ning Song , Marek A. Perkowski A New Approach to And/Or/Exor Factorization for Regular Array. [Citation Graph (0, 0)][DBLP ] Conf ] Sorin Cotofana , Stamatis Vassiliadis On the Design Complexity of the Issue Logic of Superscalar Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinori Sato Data Dependence Speculation Using Data Address Prediction and its Enhancement with Instruction Reissue. [Citation Graph (0, 0)][DBLP ] Conf ] Joan-Manuel Parcerisa , Antonio González The Latency Hiding Effectiveness of Decoupled Access/Execute Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Johnny Öberg , Peeter Ellervee Revolver: A High-Performance MIMD Architecture for Collision Free Computing. [Citation Graph (0, 0)][DBLP ] Conf ] J. A. Maestro , Daniel Mozos , Julio Septién A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign Proces. [Citation Graph (0, 0)][DBLP ] Conf ] Apostolos A. Kountouris , Christophe Wolinski Hierarchical Conditional Dependency Graphs for Conditional Resource Sharing. [Citation Graph (0, 0)][DBLP ] Conf ] Ludovic Jacomme , Frédéric Pétrot , Rajesh K. Bawa Formal Extraction of Memorizing Elements for Sequential VHDL Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro Marcuello , Antonio González Data Speculative Multithreaded Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Tate , Gordon Steven , Paul Findlay The Impact of a Realistic Cache Structure on a Statically Scheduled Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Peter-Michael Seidel How to Half the Latency of IEEE Compliant Floating-Point Multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Julio Sahuquillo , Ana Pont Impact of Reducing Miss Write Latencies in Multiprocessors with Two Level Cache. [Citation Graph (0, 0)][DBLP ] Conf ] Fenghao Mu , Christer Svensson Efficient High-Speed CMOS Design by Layout Based Schematic Method. [Citation Graph (0, 0)][DBLP ] Conf ] Per Larsson-Edefors A Miniature Serial-Data SIMD Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Ramon Doallo , Basilio B. Fraguela , Emilio L. Zapata Cache Probabilistic Modeling for Basic Sparse Algebra Kernels Involving Matrices with a Non Uniform Distribution. [Citation Graph (0, 0)][DBLP ] Conf ] Jonas Hallberg , Zebo Peng Estimation and Consideration of Interconnection Delays during High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Werner Grass , Stefan Lenk , Christine Sontheim Design of Control Dominated Hardware Based on Formal Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Anatoli Sergyienko , Juri Kanevski , Oleg Maslennikov , Roman Wyrzykowski A Method for Mapping DSP Algorithms into Application Specific Structures. [Citation Graph (0, 0)][DBLP ] Conf ] G. Latif-Shabgahi , Julian M. Bass , Stuart Bennett Simulation of a Component-Oriented Voter Library for Dependable Control Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Vincenzo De Florio , Geert Deconinck , Rudy Lauwereins The EFTOS Voting Farm: A Software Tool for Fault Masking in Message Passing Parallel Environments. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Feldt Generating Multiple Diverse Software Versions with Genetic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Luís Moura Silva , João Gabriel Silva An Experimental Study about Diskless Checkpointing. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Zambonelli Distributed Checkpoint Algorithms to Avoid Roll-Back Propagation. [Citation Graph (0, 0)][DBLP ] Conf ] R. Stroph , T. Clarke Dynamic Acceptance Tests for Complex Controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Gil , J. C. Baraza , J. V. Busquets , Pedro J. Gil Fault Injection into VHDL Models: Analysis of the Error Syndrome of a Microcomputer System. [Citation Graph (0, 0)][DBLP ] Conf ] Maximilian Frey , Bernd-Holger Schlingloff On-the-Fly Model Checking of Program Runs for Automated Debugging. [Citation Graph (0, 0)][DBLP ] Conf ] Mats Per Erik Heimdahl , Jeffrey M. Thompson , Michael W. Whalen On the Effectiveness of Slicing Hierarchical State Machines: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Peter R. Croll , Chris Rudram , Colin Chambers , Naoshi Uchihira Engineering Safe, Real-Time Distributed Control Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Roman Gumzej , Matjaz Colnaric , Domen Verber , Wolfgang A. Halang Towards Standard-Based Specification and Design of Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] A. Maamar , G. Russell A 32-Bit Risc Processor with Concurrent Error Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Holger Karl , Matthias Werner , Lars Küttner An Experimental Investigation of Message Latencies in the Totem Protocol in the Presence of Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Kam-yiu Lam , Tony S. H. Lee Approaches for Scheduling of Triggered Transactions in Real-Time Active Database Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Marjeta Frey-Pucko , Maximilian Frey Multi-View Specification of CSCW Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Cyril Decleir , Mohand-Said Hacid , Jacques Kouloumdjian Modeling and Querying Video Databases. [Citation Graph (0, 0)][DBLP ] Conf ] F. Calzolari , Paolo Tonella Modeling Client/Server Interactions by Means of Dynamic Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Ming Huang , Chian Wang , Cheng-Yi Kuo A Master-Medium-Based Interactive Synchronization Control Scheme for Distributed Multimedia Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Weeks , Hadj Batatia , Reza Sotudeh Improved Multimedia Server I/O Subsystems. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Chang Chen , Chein-Chih Chang , Wen-Shyong Hsieh , Chu-Sing Yang Address Resolution Model and Traffic Control for Multimedia Data Transmission with QoS Guarantees between ATM and Ethernet. [Citation Graph (0, 0)][DBLP ] Conf ] D. Papadimatos , Theodore Antonakopoulos , Vassilios Makios Real-Time Disparity Information Compression in 3D Teleconferencing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Silvello Betti , E. Bravi , M. Giaconi Comparison between Optical SCM Systems for Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Belloum , Louis O. Hertzberger Dealing with One-Timer-Documents in Web Caching. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto García-Martínez , Jesús Fernández-Conde , Ángel Viña Efficient Memory Management in VOD Disk Array Servers Using Per-Storage-Device Buffering. [Citation Graph (0, 0)][DBLP ] Conf ] Stamatis Vassiliadis , E. A. Hakkennes , J. S. S. M. Wong , Gerald G. Pechanek The Sum-Absolute-Difference Motion Estimation Accelerato. [Citation Graph (0, 0)][DBLP ] Conf ] Kimmo Kaario , Pertti Raatikainen Dimensioning of a Multimedia Switching Bus. [Citation Graph (0, 0)][DBLP ] Conf ] Sugh-Hoon Lee , Sungyoung Lee Retransmission Scheme for MPEG Streams in Mission Critical Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo Magaña , Javier Aracil , Jesús E. Villadangos PROMIS: A Reliable Real-Time Network Management Tool for Wide Area Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jeong-Gook Koh , Gil-Yong Kim Design and Performance Evaluation of a Buffer Replacement Algorithm Utilizing Reference Interval Information. [Citation Graph (0, 0)][DBLP ] Conf ] Gaetano Vespasiano , Maria Stella Iacobucci , Pasquale Palma Broadband Services in the Access Network: A Technical-Economic Comparison of Wired and Wireless Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Eng Huat Ng , Stu Wade Designing Interactive Multimedia Learning Systems on the Web Using a New Graphical Navigational Design Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Seungtaek Oh , Yung Yi , Seunghoon Jeong , Yanghee Choi , Younghwa Ko Experiments with MHEG Player/Studio: An Interactive Hypermedia Visualization and Authoring System. [Citation Graph (0, 0)][DBLP ] Conf ] Perfecto Mariño , Miguel Angel Domínguez Integration of Image Processing and Automated Testing in a Manufacturing Client-Server Network. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios I. Rigas , James L. Alty Using Sound to Communicate Program Execution. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitris A. Karras , S. A. Karkanis , Basil G. Mertzios Image Compression Using the Wavelet Transform on Textural Regions of Interest. [Citation Graph (0, 0)][DBLP ] Conf ] Bob Newman A Methodology for Design of Large Hypermedia Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Nigel Steele , A. Dobnikar Novel Internal Units for a Neural Network Based Adaptive Fuzzy Inference Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas König , Michael Eberhardt , Robert Wenzel A Transparent and Flexible Development Environment for Rapid Design of Cognitive Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ion Ciuca On Function Approximators Implementable as Layered Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitris A. Karras , I. J. Marmatsouri , E. J. Hatzakis , N. Paritsis On Feature Selection Methods in the Application of Neural Networks to Social Sciences. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Glösekötter , Andreas Kanstein , Stefan Jung , Karl Goser Implementation of a RBF Network Based on Possibilistic Reasoning. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitris A. Karras , Isaac E. Lagaris A Novel Neural Network Training Technique Based on a Multi-Algorithm Constrained Optimization Strategy. [Citation Graph (0, 0)][DBLP ] Conf ] David Abramson , Kate A. Smith , Paul Logothetis , David Duke FPGA Based Implementation of a Hopfield Neural Network for Solving Constraint Satisfaction Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Harald Wüst , Klaus Kasper , Herbert Reininger Hybrid Number Representation for the FPGA-Realization of a Versatile Neuro-Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Melquíades Pérez Pérez , Francisco Almeida , J. Marcos Moreno-Vega Genetic Algorithm with Multistart Search for the p-Hub Median Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Yannick Monnier , Jean-Pierre Beauvais , Anne-Marie Déplanche A Genetic Algorithm for Scheduling Tasks in a Real-Time Distributed System. [Citation Graph (0, 0)][DBLP ] Conf ] Gianluigi Folino , Clara Pizzuti , Giandomenico Spezzano Solving the Satisfiability Problem by a Parallel Celluar Genetic Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] José Mira , Juan Carlos Herrero , Ana E. Delgado García Where is Knowledge in Computational Intelligence?: On the Reduction of the Knowledge Level to the Level Below. [Citation Graph (0, 0)][DBLP ] Conf ] Tony Y. T. Chan A Fast Metric Approach to Feature Subset Selection. [Citation Graph (0, 0)][DBLP ] Conf ] Samuel Túnez , Roque Marín , Isabel María del Águila , Alfonso Bosch , Manuel Torres An Abductive Method for Solving a Treatment Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Jouni Raitamäki Improving the Performance of Fuzzy Systems by Using Local Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Xavier Franch , Josep M. Ribó Balust A Structured Approach to Software Process Modelling. [Citation Graph (0, 0)][DBLP ] Conf ] Tapani Kilpi Towards Continuous Process Development: Designing SQA Function for Large Organisation Needs. [Citation Graph (0, 0)][DBLP ] Conf ] Akif Günes Koru , Elif Demirörs , Onur Demirörs Process-Product Unification in a Decentralized Environment: A Status Report. [Citation Graph (0, 0)][DBLP ] Conf ] R. Maier Process Improvement by Change of Paradigm in an Agriculture Company. [Citation Graph (0, 0)][DBLP ] Conf ] W. Lam , V. Shankararaman Managing Change in Software Development Using a Process Improvement Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Emilio Benedetti , Luisa Consolini CMOS - Change Management Of Software ESSI PIE nr. 23661. [Citation Graph (0, 0)][DBLP ] Conf ] Ivica Crnkovic A Change Process Model in an SCM Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Winokur , Arie Grinman , Israel Yosha , Reuven Gallant Measuring the Effectiveness of Introducing New Methods in the Software Development Process. [Citation Graph (0, 0)][DBLP ] Conf ] Volkmar H. Haase Software Process Improvement Planning with Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Ignac Lovrek , Vjekoslav Sinkovic , Dejan Grahovac , Antun Caric An Approach to Schedule Estimation and Tracking for Rapid Development Projects. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus D. Zesar , Michael Zechner , Peter Salhofer , Gerhard Schuster , Gerfried Muelleitner Performance and Quality Aspects of Virtual Software Enterprises. [Citation Graph (0, 0)][DBLP ] Conf ] Hareton K. N. Leung Test Tools for the Year 2000 Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Mazen Malek , Sarolta Dibuz Pragmatic Method for Interoperability Test Suite Derivation. [Citation Graph (0, 0)][DBLP ] Conf ] V. V. Ostapenko Test Selection Based on Implementation Specification. [Citation Graph (0, 0)][DBLP ] Conf ] Per Runeson , Peter Isacsson Software Quality Assurance - Concepts and Misconceptions. [Citation Graph (0, 0)][DBLP ] Conf ] Anne Mette Jonassen Hass , Jørn Johansen , Jan Pries-Heje Does ISO 9001 Increase Software Development Maturity?. [Citation Graph (0, 0)][DBLP ] Conf ] Janne Kiiskilä Practical Aspects on the Assessment of a Review Process. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Erik Stokke Software Development Process Improvements by Metrics - A Taming of Chaos. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Ezran , Maurizio Morisio , Colin Tully A Survey of European Reuse Experiences: Initial Results. [Citation Graph (0, 0)][DBLP ] Conf ] Ewan Smith , Adil Al-Yasiri , Madjid Merabti A Multi-Tiered Classification Scheme for Component Retrieval. [Citation Graph (0, 0)][DBLP ] Conf ] Elisabetta Morandin , Gianfranco Stellucci , Francesco Baruchelli A Reuse-Based Software Process Based on Domain Analysis and OO Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Hamann , Janne Järvinen , Andreas Birk , Dietmar Pfahl A Product-Process Dependency Definition Method. [Citation Graph (0, 0)][DBLP ] Conf ] Jorma Taramaa , Munish Khurana , Pasi Kuvaja , Jari Lehtonen , Markku Oivo , Veikko Seppänen Product-Based Software Process Improvement for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Barry McCollum , Vaughan Purnell , Patrick H. Corr , Peter Milligan The Improvement of a Software Design Methodology by Encapsulating Knowledge from Code. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Kreiner , Christian Steger , Reinhold Weiss Improvement of Control Software for Automatic Logistic Systems Using Executable Environment Models. [Citation Graph (0, 0)][DBLP ] Conf ] José R. P. Ribeiro , Nilton C. da Silva , Roxana G. Morón , Célio Estevan Morón From Design to Implementation Using the Parallel Program Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Colin Allison , Martin Bramley , Jose Serrano The World Wide Wait: Where Does the Time Go? [Citation Graph (0, 0)][DBLP ] Conf ] Gilbert Babin , Peter G. Kropf , Herwig Unger Two-Level Communication Protocol for a Web Operating System (WOS?). [Citation Graph (0, 0)][DBLP ] Conf ] Djamshid Tavangarian , Peter Eschholz , Michael Koch , Stephan Preuß Wide-Area High-Performance Computing Using Workstations. [Citation Graph (0, 0)][DBLP ] Conf ] Antônio Augusto Fröhlich , Wolfgang Schröder-Preikschat SMP PCs: A Case Study on Cluster Computing. [Citation Graph (0, 0)][DBLP ] Conf ] José L. Roda , Casiano Rodríguez , Daniel González-Morales , Francisco Almeida Bulk Synchronous Parallel without Barriers. [Citation Graph (0, 0)][DBLP ] Conf ] Bettina Schnor , Stefan Petri , Matthias Becker Scalability of Multicast Based Synchronization Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmoud Mofaddel , Djamshid Tavangarian User-Profile Adaptable Resource Management System for Workstation Cluster Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Ferenc Vajda The Pros and Cons of Web Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Eila Niemelä , Mikko Holappa Experiences with the Use of CORBA. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Polze , Lui Sha Composite Objects: Real-Time Programming with CORBA. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Obelöer , Claus Grewe , Holger Pals Load Management with Mobile Agents. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Lizzi , Eric Gressier-Soudan A Real-Time IPC Service over ATM Networks for the Chorus Distributed System. [Citation Graph (0, 0)][DBLP ] Conf ] Ali R. Hurson , Y. C. Chehadeh , Les L. Miller Object Organization on a Single Broadcast Channel in a Global Information Sharing Environment. [Citation Graph (0, 0)][DBLP ] Conf ] R. S. Fish , J. M. Graham , Roger J. Loader DRoPS: Kernel Support For Runtime Adaptable Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Dmitry Arapov , Victor Ivannikov , Alexey Kalinov , Alexey L. Lastovetsky , Ilya Ledovskih Managing Processes with Network Objects and Their Translation. [Citation Graph (0, 0)][DBLP ] Conf ] Moritz Schulé , Michael Meißner Parallelization of Volume Visualization on Computer Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Adrianos Lachanas , Paraskevas Evripidou , Silas Michaelides Regional Weather Prediction on Small Network of Workstations. [Citation Graph (0, 0)][DBLP ] Conf ] Edelhard Becker , Roland Hoyss , Thomas Grunert A System for Cooperative Work in the Medical Domain. [Citation Graph (0, 0)][DBLP ] Conf ] Manfred Glesner , Matthias Rychetsky , Stefan Ortmann Advanced Hardware and Software Architectures for Computational Intelligence: Application to a Real World Problem. [Citation Graph (0, 0)][DBLP ] Conf ] 