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Journals in DBLP

Microelectronics Reliability
2003, volume: 43, number: 8

  1. G. Ghibaudo, E. Vincent
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1173- [Journal]
  2. Ernest Y. Wu, Jordi Suñé, Wing L. Lai, Alex Vayshenker, E. Nowak, D. Harmon
    Critical reliability challenges in scaling SiO2-based dielectric to its limit. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1175-1184 [Journal]
  3. Jordi Suñé, Ernest Y. Wu, D. Jiménez, Wing L. Lai
    Statistics of soft and hard breakdown in thin SiO2 gate oxides. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1185-1192 [Journal]
  4. James H. Stathis, R. Rodríguez, Barry P. Linder
    Circuit implications of gate oxide breakdown. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1193-1197 [Journal]
  5. F. Monsieur, E. Vincent, V. Huard, S. Bruyère, D. Roy, T. Skotnicki, G. Pananakakis, G. Ghibaudo
    On the role of holes in oxide breakdown mechanism in inverted nMOSFETs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1199-1202 [Journal]
  6. M. Porti, S. Meli, M. Nafría, X. Aymerich
    Pre-breakdown noise in electrically stressed thin SiO2 layers of MOS devices observed with C-AFM. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1203-1209 [Journal]
  7. G. Ribes, S. Bruyère, F. Monsieur, D. Roy, V. Huard
    New insights into the change of voltage acceleration and temperature activation of oxide breakdown. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1211-1214 [Journal]
  8. Andreas Martin, Jochen von Hagen, Glenn B. Alers
    Ramped current stress for fast and reliable wafer level reliability monitoring of thin gate oxide reliability. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1215-1220 [Journal]
  9. G. Ghidini, A. Garavaglia, G. Giusto, A. Ghetti, R. Bottini, D. Peschiaroli, M. Scaravaggi, F. Cazzaniga, D. Ielmini
    Impact of gate stack process on conduction and reliability of 0.18 mum PMOSFET. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1221-1227 [Journal]
  10. A. Ghetti, D. Brazzelli, A. Benvenuti, G. Ghidini, A. Pavan
    Anomalous gate oxide conduction on isolation edges: analysis and process optimization. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1229-1235 [Journal]
  11. C. Besset, S. Bruyère, S. Blonkowski, S. Crémer, E. Vincent
    MIM capacitance variation under electrical stress. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1237-1240 [Journal]
  12. A. Bravaix, C. Trapes, D. Goguenheim, N. Revil, E. Vincent
    Carrier injection efficiency for the reliability study of 3.5-1.2 nm thick gate-oxide CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1241-1246 [Journal]
  13. S. Cimino, A. Cester, A. Paccagnella, G. Ghidini
    Ionising radiation effects on MOSFET drain current. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1247-1251 [Journal]
  14. Albena Paskaleva, Martin Lemberger, Stefan Zürcher, Anton J. Bauer, Lothar Frey, Heiner Ryssel
    Electrical characterization of zirconium silicate films obtained from novel MOCVD precursors. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1253-1257 [Journal]
  15. F. Mondon, S. Blonkowski
    Electrical characterisation and reliability of HfO2 and Al2O3-HfO2 MIM capacitors. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1259-1266 [Journal]
  16. Kenji Takahashi, Mitsuo Umemoto, Naotaka Tanaka, Kazumasa Tanida, Yoshihiko Nemoto, Yoshihiro Tomita, Masamoto Tago, Manabu Bonkohara
    Ultra-high-density interconnection technology of three-dimensional packaging. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1267-1279 [Journal]
  17. R. García, Magali Estrada, Antonio Cerdeira
    Effects of impurity concentration, hydrogen plasma process and crystallization temperature on poly-crystalline films obtained from PECVD a-Si: H layers. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1281-1287 [Journal]
  18. K. L. Ng, Nian Zhan, C. W. Kok, M. C. Poon, Hei Wong
    Electrical characterization of the hafnium oxide prepared by direct sputtering of Hf in oxygen with rapid thermal annealing. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1289-1293 [Journal]
  19. I-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, Ming-Dou Ker
    Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1295-1301 [Journal]
  20. J. H. Zhang, Y. C. Chan, M. O. Alam, S. Fu
    Contact resistance and adhesion performance of ACF interconnections to aluminum metallization. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1303-1310 [Journal]
  21. Y. S. Zheng, Y. J. Su, B. Yu, P. D. Foo
    Investigation of defect on copper bond pad surface in copper/low k process integration. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1311-1316 [Journal]
  22. N. Duan, J. Scheer, J. Bielen, M. van Kleef
    The influence of Sn-Cu-Ni(Au) and Sn-Au intermetallic compounds on the solder joint reliability of flip chips on low temperature co-fired ceramic substrates. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1317-1327 [Journal]
  23. Tong Yan Tee, Hun Shen Ng, Daniel Yap, Zhaowei Zhong
    Comprehensive board-level solder joint reliability modeling and testing of QFN and PowerQFN packages. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1329-1338 [Journal]
  24. Li-Rong Zheng, Johan Liu
    System-on-package: a broad perspective from system design to technology development. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1339-1348 [Journal]
  25. W. L. Pearn, Ming-Hung Shu
    Erratum to "An algorithm for calculating the lower confidence bounds of CPU and CPL with application to low-drop-out linear regulators" [Microelectronics Reliability 2003;43: 495-502]. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1349- [Journal]
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